Sony CA-702 Maintenance Manual page 86

IC
CXD8280AQ (SONY)
C-MOS DIGITAL AUDIO TIME BASE EXPANSION FOR SIF RECEIVER
—TOP VIEW—
91 GND
92
93
94
95
96
97
98
99
100
101 GND
102
103 NC
104
105 NC
106 V
DD(+5V)
107
NC
108 NC
109
110
111 GND
112
113
114
115
116 NC
117
118
V
DD(+5V)
119
120
PIN
I/O SIGNAL DESCRIPTION
NO.
1 — GND
2 I TEST
XMM
3 I CLR POWER ON CLEAR
4
O HIGH TEST (ALWAYS H)
5 O RERR TEST (R-ERROR)
6 O MON4 TEST (DELAY CH-4)
7 O
MON3 TEST (DELAY CH-3)
8 O MON2 TEST (DELAY CH-2)
9
O MON1 TEST (DELAY CH-1)
10 I OEMON OUTPUT ENABLE FOR PIN 4 - 9
11 — GND
12 I
ITA TEST
13 I ITB TEST
14
I ITC TEST
15 I ITD TEST
16 — V
DD
17 I
INTP4 CH-4 AUDIO INTERPOLATE
18 I INTP3 CH-3 AUDIO INTERPOLATE
19 I INTP2 CH-2 AUDIO INTERPOLATE
20 I CH-1 AUDIO INTERPOLATE
INTP1
21 — GND
22 I
CHEX1 CHANNEL EXCHANGE 1
23 I CHEX0 CHANNEL EXCHANGE 0
24 I AFS AUDIO FORMAT SELECT
25 I AUDIO LEFT/RIGHT BIT SELECT
LRS
26 I DIR AUDIO LSB/MSB FIRST SELECT
27
I 20/16 AUDIO 20-BIT/16-BIT SELECT
28 O WERR TEST (W-ERROR)
29 O Z3/4 CH-3/4 BLOCK SYNC (Z-FLAG)
30 O
Z1/2 CH-1/2 BLOCK SYNC (Z-FLAG)
31 — GND
32
O C3/4 CH-3/4 CHANNEL STATUS BIT
33 O C1/2 CH-1/2 CHANNEL STATUS BIT
34 O U3/4 CH-3/4 USER BIT
35 O
U1/2 CH-1/2 USER BIT
36 O V3/4 CH-3/4 VALIDITY FLAG
37
O V1/2 CH-1/2 VALIDITY FLAG
38 O CH-3/4 AUDIO DATA
AD3/4
39 O AD1/2 CH-1/2 AUDIO DATA
40 I
OEAD OUTPUT ENABLE FOR PIN 29 - 39
41 — GND
42 I BCK AUDIO BIT CLOCK
43 I AUDIO L/R CLOCK
LRCK
44 O CMYW TEST
45 —
NC
46 — V
DD
47 — NC
48 —
NC
49 I TEST TEST
50
I CRCK BUS ADDRESS LATCH CLOCK
51 — GND
52 O CRD7 BUS READ DATA 7
53 O
CRD6 BUS READ DATA 6
54 O CRD5 BUS READ DATA 5
55
O CRD4 BUS READ DATA 4
56 O BUS READ DATA 3
CRD3
57 O CRD2 BUS READ DATA 2
58 O
CRD1 BUS READ DATA 1
59 O CRD0 BUS READ DATA 0
60
— V
DD
4-8
V
DD(+5V) 60
59
58
57
56
55
54
53
52
51
GND
50
49
NC 48
NC 47
V 46
DD(+5V)
NC 45
44
43
42
GND 41
40
39
38
37
36
35
34
33
32
31
GND
V = +5 V
DD
PIN
I/O SIGNAL DESCRIPTION
NO.
— GND
61
62 I OECRD OUTPUT ENABLE FOR PIN 52 - 59
I CRA0 BUS READ ADDRESS 0
63
I CRA1 BUS READ ADDRESS 1
64
CRA2
65 I BUS READ ADDRESS 2
I CRA3 BUS READ ADDRESS 3
66
67 I CRA4 BUS READ ADDRESS 4
I CRA5 BUS READ ADDRESS 5
68
I DRA6 BUS READ ADDRESS 6
69
CREN
70 I BUS ADDRESS LATCH ENABLE
— GND
71
72 O ERROR1 CH-1 ERROR FLAG
O ERROR2 CH-2 ERROR FLAG
73
O ERROR3 CH-3 ERROR FLAG
74
ERROR4
75 O CH-4 ERROR FLAG
— V
76 DD
77 O EXIST1 CH-1 EXIST
EXIST2 CH-2 EXIST
78 O
O EXIST3 CH-3 EXIST
79
EXIST4
80 O CH-4 EXIST
— GND
81
O DIDPER DID PARITY ERROR
82
DIDERR
83 O DID UNMATCH ERROR
O DBNPER DBN PARITY ERROR
84
85 O DBNERR DBN UNCONTINUITY ERROR
O DCPER DC PARITY ERROR
86
O DCERR DC UNMATCH ERROR
87
UDPER
88 O UD PARITY ERROR
O CSERR CHECKSUM ERROR
89
90 I OEERR OUTPUT ENABLE FOR PIN 82 - 89
— GND
91
I VIDEO0 VIDEO DATA 0
92
VIDEO1
93 I VIDEO DATA 1
I VIDEO2 VIDEO DATA 2
94
95 I VIDEO3 VIDEO DATA 3
I VIDEO4 VIDEO DATA 4
96
I VIDEO5 VIDEO DATA 5
97
VIDEO6
98 I VIDEO DATA 6
I VIDEO7 VIDEO DATA 7
99
100 I VIDEO8 VIDEO DATA 8
GND
101 —
I VIDEO9 VIDEO DATA 9
102
NC
103 —
I 525/625 525/625 SELECT
104
— NC
105
V
106 — DD
— NC
107
108 — NC
— NC
109
I VCK VIDEO CLOCK
110
GND
111 —
I D2/D1 D2/D1 SELECT
112
113 I DID1 DID BIT1
I DID2 DID BIT2
114
I ERDB ERROR OVERRIDE FOR DEBUG
115
NC
116 —
O EDHF EDH FULL FIELD ERROR
117
118 O EDHA EDH ACTIVE PICTURE ERROR
O OVFS TEST
119
— V
120 DD
M62352GP (MITSUBISHI)FLAT PACKAGE
M62352GP-75ED
C-MOS 8-BIT x 12 CHANNEL D/A CONVERTER
(WITH BUFFER OPERATIONAL AMPLIFIER)
—TOP VIEW—
1 V GND 20
SS
AO3 2 19 AO2
AO4 3 18 AO1
AO5 4 17 DI
AO6 5 16 CK
AO7 6 15 LD
AO8 7 14 DO
AO9 8 13 AO12
AO10 9 12 AO11
V
CC
10 V 11
DD
(+5V)
AO1 - AO12 ; 8-BIT D/A OUTPUTS
CK ; CLOCK INPUT
DI ; SERIAL DATA INPUT
DO ; DATA OUTPUT
NOTE:
3.5 V < V < V
DD CC
_3.5 V < V < V
SS CC
17
DI
12-BIT SHIFT RESISTOR
16
CK
15 ADDRESS
LD
DECODER
8 CH1
8 8-BIT
LATCH
D/A CONVERTER
12
CH2
CH3
CH4
CH5
CH6
CH7
CH8
CH9
CH10
CH11
CH12
15
LD
17 18
DI AO1
19
AO2
2
AO3
3
AO4
4
AO5
5
AO6
6
AO7
7
AO8
8
AO9
9
AO10
11
AO11
12
AO12
16 14
DO
14
DO
8-BIT
+
18
AO1
–
19
AO2
2
AO3
3
AO4
4
AO5
5
AO6
6
AO7
7
AO8
8
AO9
9
AO10
12
AO11
13
AO12
CA-702
CA-702P