Pcie Interface; Figure 3-5 Recommended Circuit Of The Pcie Interface(Cp Only) - Samsung SA-N9001 Hardware Manual

Hardware Guide

3.5 PCIe Interface

The module provides PCIe interface.
It is compliant to PCI Express Base 3.0 Specification, revision 1.0
It supports the Gen4 (5Gbps)
It supports each 1-lane for TX and RX.
It supports dynamic frequency configuration
It has a 16-bit PIPE width per lane.
It supports PCIe Active State Power Management (ASPM) including L1 sub state
It has a dedicated DBI Slave IF.
It supports Internal ATU (Address Translation Unit)
It supports AXI3 Bridge.
It supports Maximum of 32 outbound requests for Non-Posted (NP)
It is recommended that the differential clock output signals of PCIe interface should be connected as Figure 3-5. Two
220nF capacitors inner module are separately placed on the TX signal in series. In addition, two 220nF capacitors
placed on the differential clock output signals in series are used for DC blocking.

Figure 3-5 Recommended circuit of the PCIe interface(CP only)

© SAMSUNG Electronics Co., Ltd. Confidential & Proprietary 33 / 79