Samsung SA-N9001 Hardware Manual page 18

Table of Contents

Advertisement

L33
PCIE1_REFCLK_N
L35
PCIE1_REFCLK_P
J33
PCIE1_RXD_N
J35
PCIE1_RXD_P
K34
PCIE1_TXD_N
K36
PCIE1_TXD_P
N29
PCIE1_CLK_REQ_N
H9
PCIE1_RST_N_RC
O36
PCIE2_REFCLK0_N
O34
PCIE2_REFCLK0_P
M34
PCIE2_RX0_N
M36
PCIE2_RX0_P
N33
PCIE2_TX0_N
N35
PCIE2_TX0_P
N31
PCIE2_CLK_REQ_N
M30
PCIE2_RST_N
SPI Interface
Q12
CP_SPI_CLK
Q10
CP_SPI_CSN
R11
CP_SPI_MISO
R9
CP_SPI_MOSI
AP / MCU ↔ CP Interface
Q26
CP_PMIC_PWR_EN
C28
CP_RESETB
F31
CP_CLK_32K
I2S Interface
C6
SPEECH_I2S_BCK_CP
C8
SPEECH_I2S_D_IN_CP
B9
SPEECH_I2S_D_OUT_CP
B7
SPEECH_I2S_LRCK_CP
B13
CP_I2S1_BCK_RSV
B11
CP_I2S1_DIN_RSV
C12
CP_I2S1_DOUT_RSV
C10
CP_I2S1_LRCK_RSV
© SAMSUNG Electronics Co., Ltd. Confidential & Proprietary
0.85
B
-
0.85
B
-
0.85
O
-
0.85
O
-
0.85
I
-
0.85
I
-
1.8
B
PU
1.8
O
0.85
B
-
0.85
B
-
0.85
O
-
0.85
O
-
0.85
I
-
0.85
I
-
1.8
B
PU
1.8
O
-
1.8
I/O
-
1.8
I/O
-
1.8
O
-
1.8
I
-
1.8
I
-
1.8
I
-
1.8
I
-
1.8
I
-
1.8
I
-
1.8
O
-
1.8
I
-
1.8
I
-
1.8
I
-
1.8
O
-
1.8
I
-
AP_PCIe0_REFCLK_N
PCIE REF CLKN
AP_PCIe0_REFCLK_P
PCIE REF CLKP
PCIE TXDN at CP
AP_PCIe0_RX_N
side
PCIE TXDP at CP
AP_PCIe0_RX_P
side
PCIE RXDN at CP
AP_PCIe0_TX_N
side
PCIE RXDP at CP
AP_PCIe0_TX_P
side
PCIE Clock
NAD_PCIe_CLK_REQn
Request_N
Leave this pin
PCIE Reset as NAD
open(floating)
Leave this pin
PCIE REF CLKN
open(floating)
Leave this pin
PCIE REF CLKP
open(floating)
Leave this pin
PCIE TXDN at CP
side
open(floating)
Leave this pin
PCIE TXDP at CP
side
open(floating)
Leave this pin
PCIE RXDN at CP
side
open(floating)
Leave this pin
PCIE RXDP at CP
side
open(floating)
Leave this pin
PCIE Clock
Request_N
open(floating)
Leave this pin
PCIE Reset as NAD
open(floating)
NAD_SPI_CLK
SPI Clock
NAD_SPI_CSn
SPI Chip Select
NAD2_SPI_MISO(slave
SPI TX DATA
NAD_SPI_MOSI(master
mode)/ AP2CP_DUMP_NOTI
NAD2_SPI_MISO(slave
SPI RX DATA
NAD_SPI_MOSI(master
NAD_PMIC_EN
CP Power on input
External Reset
Input
CP sleep clock /
input
NAD_I2S_BCK
Audio I/F Clock
Audio I/F Serial
NAD_I2S_DIN
Data Input
Audio I/F Serial
NAD_I2S_DOUT
Data Output
Audio I/F
NAD_I2S_LRCK
Left/Right Channel
Leave this pin
Audio I/F Clock
open(floating)
Leave this pin
Audio I/F Serial
Data Input
open(floating)
Leave this pin
Audio I/F Serial
Data Output
open(floating)
Leave this pin
Audio I/F
Left/Right Channel
open(floating)
AP_PCIe0_REFCLK_N
AP_PCIe0_REFCLK_P
AP_PCIe0_RX_N
AP_PCIe0_RX_P
AP_PCIe0_TX_N
AP_PCIe0_TX_P
NAD_PCIe_CLK_REQn
NAD_PCIe_RSTn
PCIE2_REFCLK0_N
PCIE2_REFCLK0_P
PCIE2_RX0_N
PCIE2_RX0_P
PCIE2_TX0_N
PCIE2_TX0_P
PCIE2_CLK_REQ_N
PCIE2_RST_N
NAD_SPI_CLK
NAD_SPI_CSn
NAD2_SPI_MISO(slave
mode)
NAD_SPI_MOSI(master
NAD2_SPI_MISO(slave
mode)
NAD_SPI_MOSI(master
mode)
NAD_PMIC_EN
NAD_RSTn
NAD_RSTn
NAD_RTC
NAD_RTC
NAD_I2S_BCK
NAD_I2S_DIN
NAD_I2S_DOUT
NAD_I2S_LRCK
CP_I2S1_BCK
CP_I2S1_DIN
CP_I2S1_DOUT
CP_I2S1_LRCK
mode)
mode)
mode)
mode)
18 / 79

Advertisement

Table of Contents
loading

Table of Contents