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Chapter 3
K7 CLK_CTL Select
Durng Optimal, this item will auto-detect the processor clock generator. Dur-
ing None, the processor clock will always be set to 100MHz. Setting options:
[Optimal] [None]. Default value: [Optimal]
SDRAM ECC Setting
This allows you to set the SDRAM Error Correcting Code. Setting options:
[Disabled] [Check Only] [Correct Errors] [Correct+Scrub]. Default value:
[Disabled]
Super Bypase Mode
When enabled, the chipset internally bypass certain memory to CPU
pipe stages for optimal performance. Setting options: [Disabled] [Enabled].
Default value: [Enabled]
SDRAM Timing by SPD
When "Enabaled", the SDRAM configures items by reading the contents in
the SPD (Serial Presence Detect) device. Setting options: [Enabled] [Disabled]
Default value: [Enabled].
3-14
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