Pll Ratio (Pllspeed) - Fujitsu FR Series Application Note

Chapter 3 User Clock Settings (CLOCKSPEED == CLOCK_USER)

3.2 PLL ratio (PLLSPEED)

The PLL multiplier can be configured individually, but there are recommended settings which
should be used. The table below gives some recommendations. Please check the data
sheet and the hardware manual for updated values.
Main Clock SV
Cntr.
Main Logic
Oscillator
1
4 MHz
0 CSVCR_
MSVE
Sub
Oscillator
Sub Clock SV
0
32 kHz
1
CSVCR_
SSVE
Cntr.
RC Logic
Oscillator
CSVCR
100 kHz
RC
0
Oscillator
2 MHz 1 CSCFG_
RCSEL
Available settings for PLLSPEED:
- Main clock 4 MHz:
Name Setting
PLLSPEED
PLLx3 0x0B02
PLLx4 0x0903
PLLx5 0x0704
PLLx6 0x0505
PLLx7 0x0306
PLLx8 0x0307
PLLx9 0x0308
PLLx10 0x0309
PLLx11 0x010A
PLLx12 0x010B
PLLx13 0x010C
PLLx14 0x010D
PLLx15 0x010E
PLLx16 0x010F
PLLx17 0x0110
PLLx18 0x0111
PLLx19 0x0112
PLLx20 0x0113
PLLx21 0x0114
PLLx22 0x0115
MCU-AN-300021-E-V10
Start91460.asm
1/2
PLL Interface x1, x2, ...x25
1/G
Auto-Gear
PLL
CLKVCO
x 1/M
1/N
FB CLKPLLFB
0
Multiplier
PLLDIVM, PLLDIVG, PLLMULG, PLLCTRL
1
CSVCR_
SCKS
Resulting Base
Clock
12 MHz
16 MHz
20 MHz
24 MHz
28 MHz
32 MHz
36 MHz
40 MHz
44 MHz
48 MHz
52 MHz
56 MHz
60 MHz
64 MHz
68 MHz
72 MHz
76 MHz
80 MHz
84 MHz
88 MHz
CLKPLL
Clock
0
1
Modulator 1
CMCR, CMPR 2
0
CMCR_ 3
FMOD
0
3
1 CANPRE_
CPCKS
Remark
Not: MB91V460A, MB91464A,
MB91465K, MB91463N, MB91467R
Not: MB91V460A, MB91464A,
MB91465K, MB91463N, MB91467R
- 16 - © Fujitsu Microelectronics Europe GmbH
Main Oscillation
Sub Oscillation
RC Oscillation 100 kHz
Main Clock / 2
Sub Clock
Φ
Base Clock
Ext. Bus Clock
CLKT
Divider /1 .. /16
DIV1R
Peripheral Clock
CLKR_
CLKP
CLKS
Divider /1 .. /16
DIV0R
CPU Clock
CLKB
Divider /1 .. /16
DIV0R
CAN Clock
CANCLK
Divider /1 .. /16
CANPRE