Closing The Ibert Demonstration; Superclock-2 Frequency Table - Xilinx Virtex-7 FPGA VC7203 Getting Started Manual

X-Ref Target - Figure 1-19
Additional information on the Vivado Design Suite software and IBERT core can be found
in Vivado Design Suite User Guide: Programming and Debugging (UG908) and LogiCORE IP
Integrated Bit Error Ratio Tester (IBERT) for 7 Series GTX Transceivers Product Guide for Vivado
Design Suite (PG132).

Closing the IBERT Demonstration

To stop the IBERT demonstration:
1.
2.

SuperClock-2 Frequency Table

Table 1-2
read-only-memory (ROM).
Table 1-2: Si570 and Si5368 Frequency Table
Address Protocol
100GE/40GE/10
0
GE
1 Aurora
2 Aurora
3 Aurora
4 Aurora
5 CE111
VC7203 IBERT Getting Started Guide
UG847 (v3.0) July 10, 2013
Figure 1-19: Serial I/O Analyzer Links
Close the Vivado Design Suite application by selecting File > Exit.
Place the main power switch SW1 in the off position.
lists the addresses for the frequencies that are programmed into the SuperClock-2
Frequency
Address
(MHz)
161.130 30
81.250 31
162.500 32
325.000 33
650.000 34
173.370 35
www.xilinx.com
Frequency
Protocol
(MHz)
OBSAI 307.200
OBSAI 614.400
OC-48 19.440
OC-48 77.760
OC-48 155.520
OC-48 311.040
SuperClock-2 Frequency Table
Frequency
Address Protocol
(MHz)
60 XAUI 156.250
61 XAUI 312.500
62 XAUI 625.000
63 Generic 66.667
64 Generic 133.333
65 Generic 166.667
23