Ml501 Demonstrations In Linear Flash; Linear Flash Lcd Demonstration; Description; Setup - Xilinx ML501 Getting Started Tutorial

For evaluation platform
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ML501 Demonstrations in Linear Flash

Linear Flash LCD Demonstration

Description

This demonstration shows the FPGA being configured by an external linear flash device
and a CPLD. This method of download is used in some embedded processor systems
where it is necessary to keep software and bitstream data in one non-volatile device.

Setup

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My Own Linear Flash Image Demonstration

Description
This exercise shows you how to store your own design into linear flash and how to
program it onto the FPGA. This exercise overwrites the contents of linear flash.
To program your own bit file into linear flash:
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2.
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To store at a specific configuration, look up the specific configuration below:
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www.BDTIC.com/XILINX
ML501 Getting Started Tutorial
UG228 (v1.0) August 30, 2006
To load a pre-loaded bitstream, change to the corresponding address configuration /
mode dip switches listed below.
Configuration 0: 00001001
Configuration 1: 00101001
Configuration 2: 01001001
Configuration 3: 01101001
Press the Prog button.
After the bitstream has loaded, the character LCD should say "Design #x Loaded using
Flash," where x is the bitstream number.
Open a DOS command shell. Click Start Menu → Run, then enter cmd as the program
to run, and click OK.
Change directory to your lab directory. Type cd <LAB_DIR>.
Copy your bit file into this folder.
Copy <file_name>.bit .
Create a BIN file, which will be used to program the linear flash device.
promgen -w -p bin -o <file_name>.bin -u 0 <file_name>.bit
Program the linear flash device with your bin file.
configuration 0: type
configuration 1: type
configuration 2: type
configuration 3: type
Change the configuration address /mode to your configuration to load your bit file.
configuration 0 : DIP switch = 00001001
configuration 1 : DIP switch = 00101001
configuration 2 : DIP switch = 01001001
configuration 3 : DIP switch = 01101001
Press prog to program the FPGA. Your design should now be running.
www.xilinx.com
ML501 Demonstrations in Linear Flash
jtagflasher -b 10 0
jtagflasher -b 10 0x800000
jtagflasher -b 10 0x1000000 <file_name>.bin
jtagflasher -b 10 0x1800000 <file_name>.bin
<file_name>.bin
<file_name>.bin
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