Sony DXC-S500 Service Manual page 65

MD8415B (FMD)
IEEE 1394 LINK-LAYER CONTROLLER CHIP
—TOP VIEW—
109
110
115
120
125
130
135
140
144
PIN PIN PIN
I/O SIGNAL I/O SIGNAL
NO. NO. NO.
O
1 — GND 37 73
ASYNCFLG
INT2
38 I 74
2 O
ITSYNC
INT1
O
O 39 75
3 CYCLEOUT
40 — 76
4 I DREQ
GND
DACK
41 I/O 77
5 I D7
CS
I/O
6 I 42 78
D6
UWE
43 — 79
7 I
V
CC
I/O
— 44 80
8 GND D5
UBE
45 I/O 81
9 I
D4
WR
—
I 46 82
10 GND
RD
I/O
11 I 47 83
D3
48 I/O 84
12 I HA7
D2
—
13 I 49 85
HA6 V
CC
50 I/O 86
14 — V
CC D1
I/O
I 51 87
15 HA5 D0
52 — 88
16 I HA4
GND
53 I/O 89
17 I HA3 CTL1
I/O
18 I HA2 54 90
CTL0
55 — 91
19 I HA1
V
CC
I
— 56 92
20 GND SCLK
57 — 93
21 I HA0
GND
58 O 94
22 O SCL LREQ
—
23 I/O SDA 59 95
V
CC
60 O 96
24 — V
CC LPS
I
— 61 97
25 SCANEN DIRECT
62 — 98
26 — EG TEST
GND
I MASTER
— 63 99
27 SKIPCONFIG
BE1
O
28 — GND 64 100
BE0
65 O 101
29 — ROMTEST
O
30 — 66 102
OSC TEST2 SYNC1
67 O 103
31 — TESTEN
SYNC0
—
I/O 68 104
32 GPIO1 V
CC
69 O 105
33 I/O GPIO0
BUSRST
IRERR
70 O 106
34 —
V
CC
IRCV IRPKT
RESET O
35 I 71 107
/
IRX
72 I/O 108
36 O ISOFLG
DXC-S500 (E)
72
70
65
60
55
50
45
40
37
PIN
I/O SIGNAL I/O SIGNAL
NO.
I/O 109 —
ICLK GND
—
110 I/O
GND HD29/ADATA13
I/O I/O
111 HD28/ADATA12
IDATA15
I/O
112 I/O
IDATA14 HD27/ADATA11
I/O I/O
113
IDATA13 HD26/ADATA10
I/O 114 I/O
IDATA12 HD25/ADATA9
I/O —
115
IDATA11 V
CC
— I/O
116 HD24/ADATA6
V
CC
I/O
117 I/O
IDATA10 HD23/ADATA7
I/O I/O
118
IDATA9 HD22/ADATA6
I/O
119 I/O
IDATA8 HD21/ADATA5
I/O I/O
120
IDATA7 HD20/ADATA4
I/O 121 —
IDATA6 GND
—
122 I/O
GND HD19/ADATA3
I/O I/O
123 HD18/ADATA2
IDATA5
I/O
124 I/O
IDATA4 HD17/ADATA1
I/O I/O
125
IDATA3 HD16/ADATA0
I/O 126 I/O
IDATA2 HD15
I/O
127 —
IDATA1 V
CC
— I/O
128 HD14
V
CC
I/O
129 I/O
IDATA0 HD13
ITX
I/O I/O
130
HD12
I ITEOP
131 I/O
HD11
ITREQ ITEN
I/O I/O
132
/ HD10
O —
133 GND
CT
—
134 I/O
GND HD9
O I/O
135
ICS HD8
I ARX
136 I/O
HD7
ARPKT
O I/O
137
HD6
ATEOP
I 138 I/O
HD5
ATX
I
139 —
V
CC
— I/O
140 HD4
V
CC
O ATEN
141 I/O
HD3
I I/O
142
ACLK HD2
I/O 143 I/O
HD31/ADATA15 HD1
I/O
144 I/O
HD30/ADATA14 HD0
INPUTS
ACLK : ASYNCHRONOUS BUS MASTER CLOCK
ARX
: ASYNCHRONOUS BUS RECEIVE DATA ENABLE
ATEOP
: ASYNCHRONOUS BUS TRANSMISSION DATA END ENABLE
ATX
: ASYNCHRONOUS BUS TRANSMISSION DATA ENABLE
CS
: CHIP SELECT
DACK
: DATA ACKNOWLEDGE
DIRECT : PHY I/F DIRECT SELECT
DREQ : DATA REQUEST
HA0 - HA7 : HOST ADDRESS
ITEOP
: ISOCHRONOUS TRANSMISSION PACKET END
ITSYNC : SYNC CONTROL
MASTER
: ISOCHRONOUS BUS CONTROLLER/CONTROLLED MODE
RD
: READ ENABLE
RESET
: RESET
SCLK : MASTER CLOCK
UBE
: UPPER BYTE ENABLE
UWE
: UPPER WORD ENABLE
WR
: WRITE ENABLE
OUTPUTS
ARPKT : ASYNCHRONOUS BUS RECEIVE PACKET ENABLE
ASYNCFLG : ASYNCHRONOUS FLAG
ATEN
: ASYNCHRONOUS BUS TRANSMISSION ENABLE
BE0 BE1
, : BYTE ENABLE
BUSRST : BUS RESET
CT : CYCLE TIMER ENABLE
CYCLEOUT : ISOCHRONOUS CYCLE
ICS : ISOCHRONOUS CYCLE START PACKET TRANSMISSION
INT1 INT2
, : INTERRUPT
IRCV IRPKT
/ : ISOCHRONOUS PACKET RECEIVE ENABLE
IRERR
: ISOCHRONOUS PACKET ERROR FLAG
ISOFLG : ISOCHRONOUS FLAG
LPS : LINK POWER STATUS
LREQ : LINK REQUEST
SCL : EEPROM SERIAL CLOCK
SYNC0, SYNC1 : SYNC CODE
INPUTS/OUTPUTS
CTL0, CTL1 : PHY-LINK CONTROL
D0 - D7 : PHY I/F DATA BUS
GPIO0, GPIO1 : GENERAL PURPOSE
HD0 - HD15 : HOST DATA BUS
HD16 - HD31/ADATA0 - ADATA15 : HOST DATA BUS UPPER BIT/ASYNCHRONOUS DATA BUS
ICLK : ISOCHRONOUS BUS MASTER CLOCK
IDATA0 - IDATA15 : ISOCHRONOUS DATA BUS
IRX
: ISOCHRONOUS RECEIVE DATA ENABLE
ITREQ ITEN
/ : ISOCHRONOUS TRANSMISSION REQUEST
ITX
: ISOCHRONOUS TRANSMISSION DATA ENABLE
SDA : EEPROM SERIAL DATA
OTHERS
EG TEST : TEST
OSC TEST2 : TEST
ROMTEST : TEST
SCANEN : TEST
SKIPCONFIG : TEST
TESTEN : TEST
75 - 79,
81 - 85,
87 - 91, 93
IDATA0-IDATA15
66, 67
ISOCHRONOUS I/F
SYNC0, SYNC1
69
BUSRST
99
ICS
107 - 108,
110 - 114,
116 - 120,
122 - 125
HD16 - HD31/
ADATA0 - ADATA15
100
ARX
101
ARPKT
102
ATEOP
ASYNCHRONOUS I/F
103
ATX
105
ATEN
106
ACLK
22
SCL
SERIAL EEPROM I/F
23
SDA
32, 33
GPIO0, GPIO1
35
RESET
36
ISOFLG
37
ASYNCFLG
38
ITSYNC
39
CYCLEOUT
41, 42,
44, 45,
47, 48,
50, 51
D0 - D7
53, 54
CTL0, CTL1
56
SCLK
LINK CORE
58
ITF/IRF LREQ
60
LSP
61
DIRECT
ATF/ARF
CSR
HOST I/F
7-11
IC