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TLK1501IRCP (TI)
0.6 TO 1.5 GBPS TRANSCEIVER
—TOP VIEW —
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
PIN
PIN
I/O
SIGNAL
I/O
SIGNAL
NO.
NO.
1
—
D.V
17
I
TXD14
CC
2
I
TXD3
18
—
D.GND
3
I
TXD4
19
I
TXD15
4
I
TXD5
20
I
TX EN
5
—
D.GND
21
I
LOOPEN
6
I
TXD6
22
I
TX ER
7
I
TXD7
23
—
D.V
CC
8
I
GTX CLK
24
I
ENABLE
9
—
D.V
25
I
LCKREFN
CC
10
I
TXD8
26
I
PRBSEN
11
I
TXD9
27
I
TESTEN
12
I
TXD10
28
—
D.GND
13
—
D.GND
29
O
RX ER/PRBS PASS
14
I
TXD11
30
O
RX DV/LOS
15
I
TXD12
31
O
RXD15
16
I
TXD13
32
O
RXD14
INPUTS
DINRXN, DINRXP
: SERIAL RECEIVE INPUTS
ENABLE
: DEVICE ENABLE
GTX CLK
: REFERENCE CLOCK
LCKREFN
: LOCK TO REFERENCE
LOOPEN
: LOOP ENABLE
PRBSEN
: PRBS TEST ENABLE
RREF
: REFERENCE RESISTOR
TESTEN
: TEST MODE ENABLE
TX EN
: TRANSMIT ENABLE
TX ER
: TRANSMIT ERROR CODING
TXD0 - TXD15
: TRANSMIT DATA
OUTPUTS
RX ER/PRBS PASS
: RECEIVE ERROR
RX DV/LOS
: RECEIVE DATA VALID
RXD0 - RXD15
: RECEIVE DATA
DOUTTXN, DOUTTXP
: SERIAL TRANSMIT OUTPUTS
21
LOOPEN
26
PRBSEN
20
TX EN
22
PRBS
TX ER
GENERATOR
2 - 4,
6, 7,
10 - 12,
8
10
14 - 17,
19
MUX
TXD0 - TXD15
8
10
8
GTX CLK
27
TESTEN
CONTROLS ;
24
PLL, BIAS, RX,TX
ENABLE
2:1
29
RX ER/
MUX
PR BS PASS
41
RX CLK
VERIFICATION
30
RX DV/LOS
31, 32,
COMMA
34 - 37,
DETECT
39, 40,
AND 8B/10B
10
42,
DECODING
44 - 47,
1:2
10
49 - 51
MUX
RXD0 - RXD15
COMMA
10
DETECT
AND 8B/10B
DECODING
DXC-S500 (E)
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
PIN
PIN
I/O
SIGNAL
I/O
SIGNAL
NO.
NO.
33
—
D.GND
49
O
RXD2
34
O
RXD13
50
O
RXD1
35
O
RXD12
51
O
RXD0
36
O
RXD11
52
—
A.GND
37
O
RXD10
53
I
DINRXN
38
—
D.V
54
I
DINRXP
CC
39
O
RXD9
55
—
A.V
CC
40
O
RXD8
56
I
RREF
41
O
RX CLK
57
—
A.V
CC
42
O
RXD7
58
—
A.GND
43
—
D.GND
59
O
DOUTTXN
44
O
RXD6
60
O
DOUTTXP
45
O
RXD5
61
—
A.GND
46
O
RXD4
62
I
TXD0
47
O
RXD3
63
I
TXD1
48
—
D.V
64
I
TXD2
CC
10
2:1
PARALLEL TO
10
MUX
SERIAL
10
BIAS
BIT
CLOCK
MULTIPLYING
CLOCK
SYNTHESIZER
BIT
CLOCK
INTERPOLATOR
2:1
AND
MUX
CLOCK RECOVERY
PRBS
RECOVERED
CLOCK
DATA
SERIAL TO
2:1
PARALLEL
MUX
SIGNAL DETECT
(LOS)
ICX282AQ-C (SONY)
2/3-INCH FRAME READOUT CCD IMAGE SENSOR
—TOP VIEW —
V
1
24
Ø 4
V
2
23
Ø 3A
V
3
22
Ø 3B
V
4
21
Ø 3C
V
5
20
Ø 2
NC
6
19
NC
7
18
V
8
17
Ø 1A
V
9
16
Ø 1B
V
10
15
Ø 1C
GND
11
14
GND
12
13
Gb
B
R
Gr
Gb
B
R
Gr
Gb
B
R
Gr
Gb
B
R
Gr
HORIZONTAL REGISTER
XC18V01S020C (XILINX)
CONFIGURATION PROM
—TOP VIEW—
1
D0
2
D2
CLK
3
60
DOUTTXP
TDI
4
DOUTTXN
59
TMS
5
56
RREF
TCK
6
CF
D4/
7
RESET
OE/
8
D6
9
CE
10
CE
CLK
3
10
6
TCK
CONTROL
DATA
5
TMS
AND
ADDRESS
4
JTAG
TDI
INTERFACE
17
TDO
54
DINRXP
DINRXN
53
7
CF
INPUTS
C
: SUBSTRATE BIAS
SUB
V
Ø 2A
H
, H
,
: HORIZONTAL REGISTER TRANSFER CLOCK
Ø1A
Ø1B
H
, H
V
Ø2A
Ø2B
Ø 1A
V
, V
,
: VERTICAL REGISTER TRANSFER CLOCK
Ø1A
Ø1B
V
, V
,
Ø1C
Ø2
V
L
V
, V
,
Ø3A
Ø3B
V
, V
Ø3C
Ø4
C
SUB
Ø
RG
: RESET GATE CLOCK
SUB
: SUBSTRATE CLOCK
Ø
ØSUB
OUTPUT
NC
V
: SIGNAL OUTOUT
OUT
GND
OTHERS
NC
: NO CONNECTION
H
Ø 1B
VL
: PROTECTION TRANSISTOR BIAS
V
Ø 2B
ØRG
Vcc
V
OUT
Gb
B
R
Gr
Gb
B
R
Gr
Gb
B
R
Gr
NOTE
Gb
B
*
: PHOTO SENSOR
*
R
Gr
INPUTS
CE
: CHIP ENABLE
20
Vcc
CLK
: CLOCK
RESET
OE/
: OUTPUT ENABLE/RESET
19
Vcc
TCK
: JTAG CLOCK
TDI
: JTAG DATA
18
Vcc
TMS
: JTAG MODE SELECT
17
TDO
OUTPUTS
CEO
: CHIP ENABLE
16
D1
CF
: JTAG CONFIG
D0 - D7
: DATA
15
D3
TDO
: JTAG DATA
14
D5
CEO
13
D7
12
11
GND
RESET
OE/
8
13
CEO
SERIAL
1
D0
OR
DATA
16, 2, 15, 7,
MEMORY
PARALLEL
14, 9, 12
INTERFACE
7
D1 - D7
IC
7-7
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