Sony DXC-S500 Service Manual page 64

IC
MD8408B (FMD)
IEEE 1394 PHYSICAL LAYER CONTROLLER
—TOP VIEW—
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
PIN PIN
I/O SIGNAL I/O
NO. NO.
1 I LREQ 17 —
2 — D.V 18 —
CC
3 O SCLK 19 I
4 — D.GND 20 I
5 I/O CTL0 21 —
6 I/O CTL1 22 —
7 — D.V 23 -—
CC
8 I/O D0 24 I
9 I/O D1 25 —
10 I/O D2 26 —
11 I/O D3 27 —
12 — D.GND 28 —
13 I/O D4 29 I/O
14 I/O D5 30 I/O
15 I/O D6 31 —
16 I/O D7 32 —
52
LDSEL
64
LPS
57
DIRECT
3
SCLK
1
LINK
LREQ
INTERFACE
5,6
CTL0, CTL1
8 - 11,
13 - 16
D0 - D7
59
LINKON
24
PURB
54
EN ACCEL
55
EN MULTI
60 - 62
PC0 - PC2
DISABLED0, 49, 50
DISABLED1
63
CMC
393.216 MHz CLK
19, 20
TEST0, TEST1
7-10
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
PIN PIN
SIGNAL I/O SIGNAL I/O SIGNAL
NO. NO.
D.V 33 I CPS 49 I DISABLED1
CC
D.V 34 — A.GND 50 I DISABLED0
CC
TEST0 35 — A.V 1 51 I S200
CC
TEST1 36 O TPBIAS1 52 I LDSEL
D.GND 37 O TPBIAS0 53 — D.V
D.V 38 I/O TPB1N 54 I EN ACCEL
CC
D.GND 39 I/O TPB1P 55 I EN MULTI
PURB 40 I/O TPA1N 56 I
A.GND 41 I/O TPA1P 57 I DIRECT
NC 42 I/O TPB0N 58 — D.GND
NC 43 I/O TPB0P 59 O LINKON
A.V 1 44 I/O TPA0N 60 I
CC
XEXT 45 I/O TPA0P 61 I
XTAL 46 — A.GND 62 I
AGND 47 — A.V 2 63 I CMC
CC
A.V 1 48 — D.GND 64 I
CC
CABLE
POWER
STATUS
DS-LINK
ENCODER/DECODER
TPBIAS GEN.
VOLTAGE -
CURRENT
GEN.
TRANSMITTER
&
RECEIVER
TRANSMITTER
CONTROL
&
UNIT
RECEIVER
24.576 MHz
CRYSTAL
PLL
OSCILLATOR
INPUTS
CMC
CPS
DIRECT
DISABLED0, DISABLED1
EN ACCEL
EN MULTI
LDSEL
LPS
LREQ
PC0 - PC2
PURB
S200
SR
TEST0, TEST1
OUTPUTS
LINKON
SCLK
TPBIAS0, TPBIAS1
INPUTS/OUTPUTS
CTL0, CTL1
D0 - D7
TPA0N, TPA1N,
TPA0P, TPA1P
TPB0N, TPB1N,
TPB0P, TPB1P
XEXT, XTAL
CC
SR
UPD448012GY-B70X-MJH (NEC)
PC2
PC1
PC0 8M (524288 x 16) - BIT SRAM
—TOP VIEW—
LPS
1
2
3
33
4
CPS
5
36
6
TPBIAS1
37
TPBIAS0
7
8
9
10
44
11
TPA0N
45
TPA0P
12
42 13
TPB0N
43
TPB0P 14
40
15
TPA1N
41
TPA1P
16
38
17
TPB1N
39
TPB1P 18
19
20
21
22
23
29
XEXT
30 24
XTAL
PIN
I/O SIGNAL
NO.
1 I
A15
2 I
A14
3 I A13
4 I
A12
5 I
A11
6 I
A10
7 I
A9
8 I A8
9 —
NC
10 —
NC
WE
11 I
12 I
CE2
: CONFIGURATION MANAGEMENT CAPABLE
: CABLE POWER STATUS
: PHY-LINK INTERFACE OPERATION MODE SETTING
: HARDWARE RESET DEFAULT OF DISABLED BIT
: HARDWARE RESET DEFAULT OF EN ACCEL BIT
: HARDWARE RESET DEFAULT OF EN MULT BIT
: PHY-LINK INTERFACE TIMING
: LINK POWER STATUS
: LINK REQUEST
: POWER CLASS
: EXTERNAL CAPACITOR FOR POWER UP RESET
: SPEED CHANGE
: SUSPEND/RESUME
: TEST
: LINK ON
: SYSTEM CLOCK
: CABLE BIAS
: PHY-LINK INTERFACE CONTROL
: PHY-LINK INTERFACE DATA
: ARBITRATION/STROBE OUTPUT,
ARBITRATION/SPEED SIGNAL/DATA INPUT
: ARBITRATION/SPEED SIGNAL/DATA OUTPUT,
ARBITRATION/STROBE INPUT
: OSCILLATOR
INPUTS
: ADRRESS
A0 - A18
48
CE1,
CE2 : CHIP ENABLE
47
LB, UB
: BYTE DATA SELECT
OE
46 : OUTPUT ENABLE
WE
: WRITE ENABLE
45
44
INPUTS/OUTPUTS
I/O1 - I/O16 : DATA
43
42
OTHER
41 NC : NO CONNECTION
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
PIN PIN PIN
I/O SIGNAL I/O SIGNAL
NO. NO. NO.
13 — 25 I 37
NC
A0
UB
CE1
14 I 26 I 38
LB
15 I 27 — 39
GND
OE
16 I 28 I 40
A18
17 I 29 I/O 41
A17 I/O1
18 I 30 I/O 42
A7
I/O9
19 I 31 I/O 43
A6 I/O2
20 I 32 I/O 44
A5 I/O10
21 I 33 I/O 45
A4 I/O3
22 I 34 I/O 46
A3 I/O11
23 I 35 I/O 47
A2 I/O4
24 I 36 I/O 48
A1 I/O12
I/O SIGNAL
— V
CC
I/O I/O5
I/O I/O13
I/O I/O6
I/O I/O14
I/O I/O7
I/O I/O15
I/O I/O8
I/O I/O16
— GND
— NC
I A16
DXC-S500 (E)