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3. FPGA and PROM circuits for IEEE1394 LINK (3/5 circuit)
The FPGA circuit generates the digital video signal input to IEEE1394 LINK in the former stage. The
FPGA circuit consists of a circuit that controls a FIFO memory area and memory. The data held in
memory is stored in IC663 and loaded in serial when the power is turned on.
IC662 reads image data to the FIFO memory inside IC662 by synchronizing an image clock of 12.288
MHz when the camera image data (YUV4:2:2) signal sent from DSP (IC521) on the SY-301 board is
input.
The ISO data suitable for IEEE1394 LINK is output to IDATA0 through IDATA15 in synchronization
with an PHY clock of 24.576 MHz.
In the LIVE image display mode, continuous animation image data is output. A still picture with image
size of 2560x1920 is divided into VGA size of 640x480 and intermittently transferred 16 times when it
is transferred.
H8 microcomputer buses CPUA0-8 and CPUD0-15 on the FM-84 board are connected to perform the
control described above.
IC661 is a power supply circuit. IC661 generates an FPGA core power of 3.3 V to 1.8 V.
4. IEEE1394 LINK circuit, PHY circuit, and H8 microcomputer system controller (4/5
circuit)
This circuit is designed so that the power of IEEE1394 is not supplied because pin 1 (VP) of a 6-pin
connector (CN853) for IEEE1394 is not connected.
IC867 enables the isochronous and asynchronous transmissions of IEEE1394 transmission according to
the specifications that conform to a 400 Mbps-compatible PHY physical layer for IEEE1394.
IC866 is a circuit corresponding to a 400 Mbps-compatible IEEE1394 link layer. During isochronous
and asynchronous transmission, the switching transmission or reception of the image data (IDATA) sent
from IC662 and an H8 microcomputer command is performed in IC662.
To perform the control described above, H8 microcomputer buses CPUA0-7 and CPUD0-15 are
connected for the setting of link registers and the issuing of commands.
IC856 is an eight-bit Motorola format-based microcomputer. Using the microcomputer, an IEEE1394
circuit is system-controlled and a CCU main microcomputer (ARMCPU) and IC856 are supported
systematically.
IC854 is a microcomputer reset generator. IC854 operates when a power of 3.3 V is input. It monitors a
supply voltage at all times. IC854 generates a reset signal when a voltage of 3.0 V decreases. (Low
active)
IC858 is a D/A converter that controls the adjustment on the FM-84 board. It is controlled by the serial
communication controlled from main microcomputer ARMCPU.
5. Lithium battery, rear connector, and SY-301 board connection connector (5/5 circuit)
In this circuit, the lithium battery (BT1001) stored in a lithium battery holder is supplied to timer RTC
that mounts a power of 3 V on the SY-301 board. CN1003 is an FS1 stereo mini-jack. CN1005 is a 9-
pin D-Sub connector. CN1001, CN1002, and CN852 are a 45-pin flexible flat cable connector. They are
connected with the SY-301 board using a flexible flat cable.
CN1005 and CN1006 are connected with the IF-874 board using a flexible flat cable.
6-5
DXC-S500 (E)
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