Multiple Module Synchronization - Agilent Technologies N6030A Series User Manual

Theory of Operation
Theory of Operation

Multiple Module Synchronization

Within each N6030A series AWG, the two channels are synchronized by
design. Some systems, such as phased array radar, require more than two
synchronized channels. The N6030A series AWGs are designed to support
the synchronization of up to 16 channels through the use of eight AWGs.
Synchronization of multiple modules can be achieved using either the
internal clock or an external clock.
Synchronization Using an Internal Clock
In synchronizing multiple modules using the internal clock, one unit is
designated as the Master and the other units are designated as Slave units.
The Master unit sources the
following signals: Sample clock, SYNC clock, and the Sync Marker. These
signals are all split and fed to each of the synchronized modules (the Master
as well as the Slaves).
The internal sample clock is at 1.25 GHz. The sample clock provides the
final retiming of the analog output from each AWG. Any skew in the sample
clock cable delays between the multiple modules will result in the same
skew in the analog outputs. Typically, the sample clock signal is split with a
matched passive splitter and the cable lengths are matched to better than 5
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Chapter 3