Software Control; Installation Instructions; Dac348X Evm Block Diagram - Texas Instruments DAC348 Series User Manual

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19.2MHz Reference
· LVCMOS Level
· Secondary Reference for
CDCE62005 PLL Mode
19.2MHz
TCXO
FPGA CLK
· TSW3100 or TSW1400
· LVDS AC coupled
OSTR_CLK
(LVPECL AC
Coupled)
DATA
DATA _CLK
FRAME
SYNC
PARITY
(LVDS DC Coupled)
Power
Supply
Circuits
J18
6V Only
2

Software Control

2.1

Installation Instructions

• Open folder named DAC348x_Installer_vxpx (xpx represents the latest version)
• Run Setup.exe
•
Follow the on-screen instructions
• Once installed, launch the program by clicking on the DAC348x_GUI_vxpx program in Start>Texas
Instruments DACs. The installation directory is located at C:\Program Files\Texas
SLAU432 – February 2012
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Ext. CLK Input
J9
· 1.3Vp Single Ended Max
· 1.5GHz Max
· Primary Reference
· (LVPECL AC coupled )
PRI
SEC
Y4
CDCE62005
Y3
Y * Y *
B A
DAC_CLK
(LVPECL AC
Coupled)
A
B
DAC348X
C
D
th
Note: 5
Figure 1. DAC348x EVM Block Diagram
Copyright © 2012, Texas Instruments Incorporated
Clock routing is optimized for layout depending
on the clock input pin out location.
Y * =
A
·
·
Y * =
B
·
·
Ext. CLK Output
J10
J11
FPGA CLK 2
· Required for TSW1400 interface with DAC34H84 and DAC34SH84
· LVDS AC coupled
th
5 Order LPF
th
5 Order LPF
th
5 Order LPF
th
5 Order LPF
Order LPF is bypassed by default
Software Control
Y1 for DAC3484 and DAC3482 EVMs
Y2 for DAC34H84 and DAC34SH84 EVMs
Y2 for DAC3484 and DAC3482 EVMs
Y1 for DAC34H84 and DAC34SH84 EVMs
+
J7
_
+
J6
_
DAC3482 Outputs
+
J3
_
+
J2
_
DAC348x EVM
3