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2.2.4
CDCE62005
Clock frequency control is determined by register values in the CDCE62005 Control tab. See the
CDCE62005 data sheet for detailed explanations of the register configuration to change the clock
frequency.
The following CDCE62005 outputs are critical to proper operation of the DAC348x:
•
Y
*: DAC348x DAC sampling clock. This clock is an ac coupled LVPECL. If the DAC348x is
A
configured for internal PLL mode, this will be the reference clock input for the PLL block.
– Y
* = Y1 for DAC3484 and DAC3482 EVMs
A
– Y
* = Y2 for DAC34H84 and DAC34SH84 EVMs
A
•
Y
*: DAC348x FIFO OSTR clock. This clock is an ac coupled LVPECL. The clock rate for this should
B
be at least F
DAC
– The whole OSTR clock equation needs to take account of both the Y1 CDCE62005 clock divider
ratio and the additional CDCP1803 divide-by-2 clock divider.
– This OSTR signal can be a slower periodic signal or a pulse depending on the application.
– Note: The FIFO OSTR clock should be disabled when the DAC348x is configured in PLL mode.
– Y
* = Y2 for DAC3484 and DAC3482 EVMs
B
– Y
* = Y1 for DAC34H84 and DAC34SH84 EVMs
B
•
Y3: FPGA Clock 1. This clock is an ac coupled LVDS. The clock rate for this should be
– F
/interpolation/2 for DAC3484
DAC
– F
/interpolation/4 for DAC3482, DAC34H84, and DAC34SH84
DAC
•
Y4: FPGA Clock 2. This clock is an ac coupled LVDS. This clock must be enabled when using the
DAC34H84 and DAC34SH84 with the TSW1400. The clock rate for this should be F
for DAC34H84, and DAC34SH84
SLAU432 – February 2012
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Figure 6. CDCE62005 Tab Configured for 4x Interpolation
/Interpolation/8. See the DAC348x data sheet for more details.
Copyright © 2012, Texas Instruments Incorporated
Software Control
/interpolation/4
DAC
9
DAC348x EVM
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