Basic Test Procedure With Tsw3100; Tsw3100 Overview; Test Block Diagram For Tsw3100; Tsw3100 Fpga Clock 100-Ω Lvds Termination At Pins T31 And T32 Of The Fpga - Texas Instruments DAC348 Series User Manual

Basic Test Procedure with TSW3100

4 Basic Test Procedure with TSW3100
This section outlines the basic test procedure for testing the EVM with TSW3100.
4.1

TSW3100 Overview

The TSW3100 is a high speed pattern generator board. The LVDS Bus rate is limited to 1.25GSPS, and
this limits the maximum input data rate per channel of DAC34SH84 to 625MSPS. To evaluate the
DAC34SH84 at 1.5GSPS DAC sampling rate, 4x or higher interpolation filter must be enabled. To
evaluate the DAC34SH84 at 1.5GSPS DAC sampling rate with 2x interpolation filter (i.e. 750MSPS of
input data rate per channel), the TSW1400 must be used.
See the TSW3100 user's guide (SLLU101) for more detailed explanations of the TSW3100 setup and
operation. This document assumes that the TSW3100 software is installed and functioning properly. The
TSW30SH84 needs TSW3100 operating software version 2.5 or higher with TSW3100 board Rev D (or
higher).
The DAC348xEVM sends the FPGA reference clock to the FPGA of the TSW3100EVM in LVDS format.
Therefore, a 100-Ω LVDS termination resistor is needed at the TSW3100 FPGA clock input. All the latest
TSW3100EVMs from TI have the 100-Ω termination installed at the bottom side of the board on pins T31
and T32 of the FPGA. Contact TI Application Support if the 100-Ω termination is missing and assistance is
needed for the 100-Ω installation.
Figure 15. TSW3100 FPGA Clock 100-Ω LVDS Termination at Pins T31 and T32 of the FPGA
4.2

Test Block Diagram for TSW3100

The test set-up for general testing of the DAC348x with the TSW3100 pattern generation card is shown in
Figure 16.
16
DAC348x EVM
Copyright © 2012, Texas Instruments Incorporated
www.ti.com
SLAU432 – February 2012
Submit Documentation Feedback