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Basic Test Procedure with TSW1400
3.3
Test Setup Connection
TSW1400 Pattern Generator.
1. Connect 5 V power supply to J12, 5V_IN jack of the TSW1400 EVM.
2. Connect PC's USB port to J5 USB port of the TSW1400 EVM. The cable should be a standard A to
mini-B connector cable.
DAC348xEVM
1. Connect J13 connector of DAC348xEVM to J4 connector of TSW1400 EVM.
2. Connect 6V to the J18, Power In jack of the DAC3484 EVM.
3. Connect PC's USB port to J14 USB port of the DAC348x EVM. The cable should be a standard A to
mini-B connector cable.
4. Provide a 1.3Vp, 1.5GHz max clock at J9, CLKIN SMA port of DAC348x EVM.
5. Connect the IF output port of J2, J3, J6, or J7 to the spectrum analyzer.
Table 1. DAC348xEVM Jumpers: (make sure the following jumpers are at their default setting)
Reference Designator
JP2
JP3
JP4
JP5
JP6
JP7
JP8, JP9, JP12, JP13
JP10
JP11
SJP9, SJP10, SJP11, SJP12
3.4
DAC348x Example Setup Procedure
1. Provide the clock input 1228.8 MHz at 1.5Vrms at J9 SMA Connector of the DAC348x EVM.
2. Turn on power to the board and press the reset SW1 button on the EVM
3. Press the "Reset USB Port" button in GUI and verify USB communication.
4. Select the appropriate EVM platform on the software menu.
5. Click "LOAD REGS", browse to the installation folder and load example file
"DAC3484_FDAC_1228p8MHz_4xint_NCO_30MHz_QMCon.txt". This file contains settings for 4x
interpolation with the DAC3484 running at 1228.8MSPS. Load this file and wait a couple of seconds for
the settings to go into effect. The DAC3482, DAC34H84, and DAC34SH84 equivalent example files
are also available in the installation folder.
12
DAC348x EVM
Setting
Function
1-2
DAC348x TXENABLE.
2-3
DAC348x SLEEP.
2-3
CDCE62005 Primary Input LVPECL Bias Enable.
1-2
CDCE62005 Reference Input Select.
1-2
CDCE62005 Power Down.
short
19.2MHz TCXO Enable.
short
SPI connection break point. This allows routing of SPI
connection to external system if troubleshooting is needed.
1-2
6V Input Select. Default is 6V at J18.
open
For DAC34H84/SH84 EVM only. Allows SPI and IO logic
threshold to switch among 1.8V, 2.5V, or 3.3V.
1-2
DAC348x DATACLK delay. Default is zero trace delay.
Figure 9. EVM Platform Selection
Copyright © 2012, Texas Instruments Incorporated
www.ti.com
SLAU432 – February 2012
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