Ip Video Interface Section; Board (Xks-T8110)/Net-28A Board (Xks-T8165) - Sony XVS-8000-C Service Manual

6-5.

IP Video Interface Section

6-5-1. NET-28 Board (XKS-T8110)/NET-28A Board (XKS-T8165)
The NET-28 and NET-28A boards have the following functions.
• Network interface boards for IP transmission
• Conversion of the SDI signal in the switcher to the IP signal by using NeptuneII ASIC
• Provided with eight RJ-45 connectors supporting 10GBASE-T Ethernet (4 connectors for redundancy)
• Transmission of up to 4 channels of 4K video signals with a single board (using 4-channel 10GbE signals and 16-
channel 3G SDI signals)
• NET-28 board for video signal input, NET-28A board for video signal output
Video signal block
Network input (NET-28 board)
The Network PHY (IC1501, IC2301, IC4101, IC4901) converts the 10Gbase-T signal that is input from the LAN cable
to the XAUI signal and sends the signal to the NeptuneII ASIC. The NeptuneII ASIC (IC1001, IC1801, IC3601, IC4401)
applies processes (including FEC, LLVC Encode/Decode, Network Packetize, and network synchronization) to Network
Packet. The processed Network Packet is sent to the FPGA as User IF signals (parallel video signals conforming to
SMPTE). The User IF signal sent from NeptuneII to the FPGA (IC301, IC2901) is corrected to the REF signal of the
unit by the TBC circuit in the FPGA, and is then converted to a serial signal. Then the converted signal is output to the
switcher as SDI signal.
SDI input (NET-28A board)
The SDI signal sent from the switcher to the FPGA (IC301, IC2901) is converted to parallel signal, and parallel signal
is sent to NeptuneII (IC1001, IC1801, IC3601, IC4401) as User IF signal. The User IF signal sent from the FPGA to
NeptuneII (IC1001, IC1801, IC3601, IC4401) is processed for FEC, LLVC Encode/Decode, NetworkPacketize,
Network synchronization in NeptuneII, and the processed signal is sent to the Network PHY (IC1501, IC2301, IC4101,
IC4901) as XAUI signal. The Network PHY that has received the XAUI signal outputs video signals to the LAN cable
as 10Gbase-T signals.
Control signal block
Nios 2 Processor
The Nios 2 processor in the FPGA (IC301, IC2901) totally controls boards. The Nios 2 processor's firmware stored in
the Flash Memory (IC207, IC2807) runs with the SRAM (IC206, IC2806) as working RAM.
The Nios processor has the following main functions.
• Control of FPGA's peripheral devices (temperature sensor, EEPROM, and clock device)
• Control of NeptuneII
• Communication with IP Live System Manager (recording/updating settings, reporting errors, etc.)
• Communication with the upper CPU (on the CA-92 board) through the RS-485 interface NeptuneII
NeptuneII
The main CPU of NeptuneII runs on the Linux OS. The NeptuneII's firmware stored in the eMMC (IC1201, IC2005,
IC3807, IC4601) runs with the DDR3 (IC1101, IC1901, IC3701, IC4501) as working RAM.
The NeptuneII CPU has the following main functions.
• Control of NeptuneII
• Communication with IP Live System Manager
• Communication with the Host CPU (Nios2)
• Control of Network PHY
Network PHY
The Network PHY's firmware is stored in the serial flash memory (IC1506, IC2304, IC4104, IC4904).
The Network PHY CPU has the following main function.
XVS-8000-C/XVS-8000
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