Table of Contents
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Contents
REVISION HISTORY ............................................................................................................ 2
WARRANTY AND DISCLAIMER ......................................................................................... 3
CONTENTS .......................................................................................................................... 4
1 INTRODUCTION.............................................................................................................. 6
1.1
Key Features........................................................................................................... 6
2 INTERRUPT TYPES ........................................................................................................ 7
2.1
Available Exceptions / Interrupts / Traps ................................................................. 7
2.1.1
Interrupts ................................................................................................... 7
2.1.1.1
2.1.1.2
2.1.2
Exceptions ................................................................................................. 7
2.1.2.1
2.1.3
Traps ......................................................................................................... 8
2.1.3.1
2.1.3.2
2.1.3.3
2.1.3.4
2.1.3.5
2.2
Direct Memory Access (DMA) ................................................................................. 8
2.3
Interrupt Acceptance, Levels and Modes................................................................. 9
2.4
Interrupt Latency ................................................................................................... 10
2.4.1
Context Saving / Restoring ...................................................................... 10
2.5
Registers............................................................................................................... 11
2.5.1
Processor Status (PS).............................................................................. 11
2.5.1.1
2.5.1.2
2.5.1.3
2.5.2
Table Base Register (TBR)....................................................................... 13
2.5.2.1
2.5.3
Interrupt Control Register (ICR00-63) .................................................... 13
2.5.4
Hold Request Cancel Level Register (HRCL)............................................ 13
2.6
Non-maskable Interrupt (NMI) ............................................................................... 14
3 INTERRUPT RECOMMENDATIONS AND EXAMPLES ................................................ 15
MCU-AN-300055-E-V10
INTERRUPTS
Contents
Peripheral Interrupts .................................................................. 7
Non-maskable Interrupts............................................................ 7
Undefined Instruction ................................................................. 7
INT Instruction ........................................................................... 8
INTE Instruction ......................................................................... 8
Step Trace Traps ....................................................................... 8
Coprocessor Not Found............................................................. 8
Coprocessor Error ..................................................................... 8
Interrupt Level Mask (ILM)....................................................... 11
Condition Code Register (CCR) ................................................ 12
System Condition Code Register (SCR) ................................... 12
Interrupt Vector Table .............................................................. 13
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