Controller - Operation - Xilinx Virtex-5 FPGA ML550 User Manual

R
Controller – Operation
The pixels for the LCD panel are stored in the controller data RAM. This RAM is a 65-row
by 132-column array. Each display pixel is represented by a single bit in the RAM array.
The interface to the RAM array goes through the 8-bit (DB0 – DB7) LCD interface.
Therefore, the 65-bit rows are split into eight pages of eight lines. The ninth page is a single
line page (DB0 only).
Interface designs can read from or write to the RAM array.
The display page is changed through the 4-bit page address register.
The column address (line address) is set with a two-byte register access. The line address
corresponds to the first line that is going to be displayed on the LCD panel. This address is
located in a 6-bit address register.
The RAM array is configured such that there are two characters per row (page), where each
character pair uses eight rows of the display panel.
address lines, ADC control, and LCD outputs (segments).
Table C-2: LCD Panel
DB3 DB2 DB1 DB0 Data
DB0
DB1
DB2
DB3
0 0 0 0
DB4
DB5
DB6
DB7
DB0
DB1
DB2
DB3
0 0 0 1
DB4
DB5
DB6
DB7
ML550 Networking Interfaces Platform
UG202 (v1.4) April 18, 2008
Page 0
Page 1
www.xilinx.com
Hardware Schematic Diagram
Table C-2 shows the input data bytes,
Line
Address
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
67