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Chapter 1: ML630 Board Features and Operation
Disabling FPGA Onboard Power
Figure 1-2
All TI controller PTD type voltage regulators are disabled by installing a jumper across
pins 1–2 of header J289.
FPGA Configuration
Figure 1-2
The FPGA is configured in JTAG mode only using one of the following options:
•
•
The FPGA Embedded JTAG option is chosen by connecting a USB A-to-Mini-B cable to
ML630 USB Mini-B connector J20. The USB A end of the cable plugs into the user's PC,
which hosts the Xilinx FPGA configuration software tool (either ChipScope™ Pro or
Impact) which is then used to configure the two ML630 FPGAs.
The FPGAs can also be configured through the System ACE controller by setting the 3-bit
configuration address DIP switches (SW3) to select one of eight bitstreams stored on a
CompactFlash memory card plugged into socket U46 (see
Upon power-on, the System ACE controller checks for the presence of a flash card and
loads the FPGA configuration files from it, if present.
The JTAG chain of the board is illustrated in
System ACE IC) with a JTAG interface has a bypass jumper which permits the component
to be in the chain or bypassed.
X-Ref Target - Figure 1-5
USB JTAG
Circuit
J20
U49
JTAG_TDI
FMC1_TDI_BUF
TDI
TDO
Sheet 5
Sheet 6&7
J290
FMC 1
Sheet 40
JTAG_TDO
System ACE Controller
Figure 1-2
The onboard System ACE controller (U47) allows storage of multiple configuration files on
a CompactFlash card. These configuration files can be used to program the FPGAs. The
CompactFlash card plugs into the CompactFlash card socket (U46) located directly above
the System ACE controller (which is on the bottom side of the board).
16
callout [6]
callout [16, 17, 18]
Embedded USB JTAG circuit (uses USB-A-to-Mini-B cable)
System ACE controller (utilizing a CompactFlash card loaded with bit files)
J51
FMC2_TDI
Sheet 92
Sheet 40
FMC1_TDO
J104
FMC 2
Sheet 92
Figure 1-5: ML630 JTAG Chain Diagram
callout [18]
www.xilinx.com
Figure
1-5. Each component (except the
3.3V 2.5V
U47
J101
System ACE
Sheet 5
SYSACE_TDI
TSTTDI
CFGTDO
TSTTDO
CFGTDI
FMC2_TDO
SYSACE_CFGTDI
Table 1-2, page
17).
U1_FPGA
Sheet 32
J136
FPGA1_TDI
TDI
TDO
SHT 32
FPGA1_TDO
FPGA2_TDI
U2_FPGA
Sheet 84
J137
TDI
TDO
Sheet 83
FPGA2_TDO
UG828_c1_05_081211
ML630 Board User Guide
UG828 (v1.0) September 28, 2011
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