Instruction Set - Xilinx Virtex-5 FPGA ML550 User Manual

Appendix C: LCD Interface

Instruction Set

Table C-7
Table C-7: Display Instructions
Instruction
Read display data
8-bit data specified by the column and page address can be read from the Display Data RAM. The column address is increased automatically,
thus data can be read continuously from the addressed page.
Write display data
8-bit data can be written into a RAM location specified by the column and page address. The column address is increased automatically, thus
data can be written continuously to the addressed page.
Read status
BUSY: Device is BUSY when internal operation or reset. (0=active, 1 =busy).
ADC: Indicates the relationship between RAM column address and segment driver.
ONOFF: Indicates display ON or OFF status.
RESETB: Indicates if initialization is in progress.
Display ON/OFF
Turn display ON or OFF. (1=ON, 0 = OFF)
Initial display line
Sets the line address of the display RAM to determine the initial line of the LCD display.
Set reference voltage mode
Set reference voltage register
This is a two-byte instruction. The first instruction sets the reference voltage mode. The second instruction sets the reference voltage parameter.
76
shows the instruction set for the LCD panel.
RS RW DB7 DB6
1 1
1 0
0 1 BUSY ADC
0 0 1 0
0 0 0 1
ST5 ST4 ST3
0 0 0
0 0 0
.. .. ..
1 1 1
1 1 1
0 0 1 0
0 0 x x
SV5 SV4
0 0
0 0
.. ..
1 1
1 1
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DB5 DB4 DB3
Read Data
Write Data
ONOFF RESETB 0
1 0 1
ST5 ST4 ST3
ST2 ST1 ST0
0 0 0
0 0 1
.. .. ..
1 1 0
1 1 1
0 0 0
SV5 SV4 SV3
SV3 SV2 SV1
0 0 0
0 0 0
.. .. ..
1 1 1
1 1 1
ML550 Networking Interfaces Platform
R
DB2 DB1 DB0
0 0 0
1 1 DON
ST2 ST1 ST0
Line address 0
Line address 1
..
Line address 62
Line address 63
0 0 1
SV2 SV1 SV0
SV0
0 0
1 1
.. ..
0 62
1 63
UG202 (v1.4) April 18, 2008