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Board Hardware
U37
UART0_TXD
UART0_RTS_N
UART0_RXD
UART0_CTS_N
XC2VP30
System ACE CF Controller
Board Bring-Up
ML310 User Guide
UG068 (v1.01) August 25, 2004
All manuals and user guides at all-guides.com
a UART usable with any member of the Virtex-II Pro device family. Please review the EDK
Processor IP Reference Guide for more details.
The RS-232 port directly connected to the XC2VP30 is accessible by a 10 pin header(J4). An
RS-232 mini-cable adapter included with the ML310 converts J4, 10 pin header, to a DB9
male connector. The adapter is a standard DTK/Intel IDC-10 to DB9 Male. The FPGA RS-
232 port on the ML310 is wired as a DTE and meets the EIA/TIA-574 standard
Figure 2-5
shows the RS-232 connectivity from the XC2VP30 to the DTK adapter.
.
U7
11
14
DIN1
DOUT1
10
7
DIN2
DOUT2
12
13
ROUT1
RIN1
9
8
ROUT2
RIN2
1
16
C1+
VCC
C330
0.1UF
3
2
C1-
V+
4
6
C2+
V-
C331
0.1UF
5
15
C2-
GND
MAX3232
Figure 2-5: FPGA UART and RS-232 Connectivity
Table 2-3
shows the RS-232 connections to the XCV2VP30 FPGA.
Table 2-3: FPGA RS-232 Connections
UCF Signal
XC2VP30 Pin
Name
(U37)
uart1_ctsn
B10
uart1_rtsn
G14
uart1_sin
F14
uart1_sout
F12
System ACE is the primary means of configuring the XC2VP30 on the ML310
board.Configuration of XC2VP30 is accomplished using the JTAG interface. System ACE
sits between the JTAG connector and the XC2VP30, and passes the JTAG signals back and
forth between the two. However, when System ACE is configuring the XC2VP30, it takes
control of the JTAG signals in order to configure the XC2VP30.
J4
1
COM0_TXD_N
3
COM0_RTS
COM0_RXD_N
5
COM0_CTS
7
VCC3V3
9
HEADER2X5
C326
0.1UF
VCC3V3
C327
0.1UF
C313
0.1UF
UG068_5_32_080204
Schem Signal
Name
UART0_CTS
UART0_RTS
UART0_RXD
UART0_TXD
www.xilinx.com
1-800-255-7778
USE A DTK-PINOUT IDC10
TO DB9 PLUG CABLE.
2
1
DSR
6
4
2
RTS
7
6
3
CTS
8
8
4
RI
9
10
5
RS232 DTE PINOUT
CONNECTS TO PC WITH
F/F NULL MODEL CABLE.
10 pin Header
DTK Adapter
(J4)
(DB9)
6
8
4
7
3
2
5
3
R
CD
RX
TX
DTR
GND
27
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