Ddr I; Bus Subsystem; Ddr I 2 C Serial Bus - Intel IQ80315 Board Manual

®
Intel IQ80315 I/O Processor Evaluation Platform
2
2.10.2

DDR I

®
The Intel
that communicates with Serial Presence Detect (SPD) EEPROMs on each DDR Module. These
EEPROMs are read by the host system to identify whether a module is present and to store module
configuration data. The SPD EEPROMs are addressed at 0x50, 0x51 and 0x52. After these
EEPROMs have been configured, writing to 0x30, 0x31, or 0x32 write-protects the first 128 bytes
of each EEPROM.
The IQ80315 CRB operates the DDR SDRAM I
modules cannot communicate on the I
Figure 4 shows a block diagram of the DDR SDRAM I
2
Figure 4. DDR I C Serial Bus
DDR SDRAM - I
Intel
The 80314 has a second I
dedicated solely to the parametric EEPROM on
SDRAM modules. SDRAM Module parameters
and operating characteristics are stored in this
EEPROM.
2
I C Addresses
0x50 = DIMM0 SPD EEPROM
0x51 = DIMM1 SPD EEPROM
0x52 = DIMM2 SPD EEPROM
0x30 = DIMM0 SPD write protect
0x31 = DIMM1 SPD write protect
0x32 = DIMM2 SPD write protect
2
I C DDR Module Serial Bus
24
C Bus Subsystem
80314 I/O processor companion chip DDR SDRAM interface has a dedicated I
2
C Serial Bus
SDRAM-SDA
SDRAM-SCL
2
SDRAM I C: 100 KHz
®
80314
40mm
2
C bus which is
®
Intel IQ80315 I/O Processor Evaluation Platform Board Manual
2
C bus at 100 KHz because some SDRAM
2
C bus at 400 KHz.
2
C bus.
SDA
SCL
Serial
A2
EEPROM
A1
2
I C Addr
A0
= 0x50
DDR DIMM Module - 0
0
SDA
SCL
Serial
A2
EEPROM
2
I C Addr
A1
= 0x51
A0
DDR DIMM Module - 1
1
SDA
SCL
Serial
2
I C Addr
A2
EEPROM
= 0x52 A1
A0
DDR DIMM Module - 2
2
SCL 3
GND 2
1
SDA
2
C bus
Serial Presence Detect
EEPROM present on a
WP
DDR Module
WP
WP
2
I C - Header 1
Keyed Header
for Testing