Peripheral Bus; Cpld; Bat_Stat Register Definition - Intel IQ80315 Board Manual

2.7

Peripheral Bus

®
The Intel
peripheral bus for devices such as flash, ROM, or SRAM memory. The IQ80315 CRB runs the
internal peripheral interface clock at the 80314 core clock frequency.
The CPLD buffers the peripheral bus data bus and demultiplexes the address bus. The
CompactFlash* and expansion header have 16-bit data busses and are accessed on the
PBI_AD[31:16] lines. The flash, seven-segment LEDs and LCD header have 8-bit data busses and
are accessed on the PBI_AD[31:24] lines. The rotary switch is 4-bits and returns data on the
PBI_AD[27:24] lines when read.
2.7.1

CPLD

A Xilinx* XC95144XL CPLD is used to implement glue logic needed on the IQ80315 CRB. The
CPLD functions are listed below:
•
Seven-segment LED decoder and latch
•
Reset strapping outputs
•
Battery status register
•
Product code register
•
Board stepping register
•
CPLD firmware revision register
•
Additional chip enable generation
•
CompactFlash* I/O control signals
•
PIO for reading 1-wire electronic serial number device
Section 3.2
space.
Table 4 defines the battery status register bits.
Table 4.

BAT_STAT Register Definition

Bit
0
1
2
3
4–7
®
Intel IQ80315 I/O Processor Evaluation Platform Board Manual
80314 I/O processor companion chip supports an asynchronous general-purpose
shows how the CPLD registers, chip enables, and GPIO port map into system address
Name
Battery present
Reserved
Battery enable
Reserved
Reserved
®
Intel IQ80315 I/O Processor Evaluation Platform
Definitions
0 = No DDR backup battery
1 = DDR backup battery is present
Undefined
0 = Disable DDR backup battery
1 = Enable DDR backup battery
Undefined
Undefined
17