Memory Map Setup By Redboot; Mmu Tables; Caching Policy; Memory Map With Caching Policy - Intel IQ80315 Board Manual

4.2.2

Memory Map Setup by RedBoot

Table 15
translation.
4.2.3

MMU Tables

The X, C, and B bit in the MMU page tables indicate the caching policy for a particular region. See
Table 22 ("Caching Policy" on page
the caching policy for a region. See
for the Virtual Memory Map and the caching policy setup by RedBoot.
Table 22.

Caching Policy

X C
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
Table 23.

Memory Map with Caching Policy

0x00000000–0x40000000
0x40000000–0x50000000
0x50000000–0x50100000
0x50100000–0x50110000
0x50110000–0x60000000
0x60000000–0x80000000
0x80000000–0x9EFF0000
0x9EFF0000–0x9F000000
0x9F000000–0xA0000000
0xA0000000–0xB0000000
0xB0000000–0xC0000000
0xC0000000–0xDEFF0000
0xDEFF0000–0xDF000000
0xDF000000–0xE0000000
0xE0000000–0xF0000000
0xF0000000–0xFFFFFFFF
®
Intel IQ80315 I/O Processor Evaluation Platform Board Manual
shows the system memory map after RedBoot* has setup the virtual–to–physical-address
B
0 Un-cached/un-buffered
1 Un-cached/buffered
0 Cached/buffered: Write-through, read allocate
1 Cached/buffered: Write-back, read allocate
0 Invalid—not used
1 Un-cached/buffered: No write buffer coalescing
0 Mini data-cache: Policy set by Auxiliary Control Register
1 Cached/buffered: Write back, read/write allocate
Virtual Address
®
Intel IQ80315 I/O Processor Evaluation Platform
45) for a description of how the X, C, and B bits translate into
Section 4.2.2 ("Memory Map Setup by RedBoot" on page
Description
X C B
1 1 1 SDRAM
0 1 0 FLASH/PBI
1 1 1 SRAM
0 0 0 Control Registers
0 0 0 No access
0 0 0 Un-cached SDRAM Alias
0 0 0 PCI1 MEM32
0 0 0 PCI1 I/O
0 0 0 PCI1 CFG
0 0 0 PCI1 PFM1
0 0 0 PCI1 PFM2
0 0 0 PCI2 MEM32
0 0 0 PCI2 I/O
0 0 0 PCI2 CFG
0 0 0 PCI2 PFM1
0 0 0 PCI2 PFM2
45)
Description
45