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5.5 Oscillators and Clocks
has two oscillator input/output pairs (MXI1/MXO1 and MXI2/MXO2) usable with external crystals or
ceramic resonators to provide clock inputs. The optimal frequencies for the crystals are 24 MHz
(MXI1/MXO1) and 27 MHz (MXI2/MXO2). Optionally, the oscillator inputs are configurable for use with
external clock oscillators. If external clock oscillators are used, to minimize the clock jitter, a single clean
power supply should power both the and the external oscillator circuit and the minimum CLKIN rise and
fall times must be observed. The electrical requirements and characteristics are described in this section.
The timing parameters for CLKOUT[3:1] are also described in this section. The has three output clock pins
(CLKOUT[3:1]). See
5.5.1 MXI1 (24-MHz) Oscillator
The MXI1 (typically 24 MHz, can also be 36 MHz) oscillator provides the primary reference clock for the
device. The on-chip oscillator requires an external crystal connected across the MXI1 and MXO1 pins,
along with two load capacitors, as shown in
connected only to the oscillator ground pin (V
power pin (V
DDA_PLL1
circuit shown in
Figure
MXI1/CLKIN
C1
The load capacitors, C1 and C2, should be chosen such that the equation is satisfied (typical values are
C1 = C2 = 10 pF). CL in the equation is the load specified by the crystal manufacturer. All discrete
components used to implement the oscillator circuit should be placed as close as possible to the
associated oscillator pins (MXI1 and MXO1) and to the V
C
C
1
2
C
L
(C
C
)
1
2
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Section 3.5
and
Section 3.6
) should be connected to the power supply through a ferrite bead, L1 in the example
5-5.
MXO1
Crystal
24 MHz or
C2
36 MHz
Figure 5-5. MXI1 (24-MHz) Oscillator
Digital Media System-on-Chip (DMSoC)
SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007
for more information on CLKOUT[3:1].
Figure
5-5. The external crystal load capacitors must be
). Do not connect to board ground (V
SS_MX1
V
V
SS_MX1
DDA_PLL1
L1
pin.
SS_MX1
Peripheral Information and Electrical Specifications
TMS320DM355
). Also, the PLL
SS
V
SSA_PLL1
0.1 F
1 F
99
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