Page 1 TMS320DM355 Digital Media System-on-Chip (DMSoC) ARM Subsystem User's Guide Literature Number: SPRUFB3 September 2007...
Page 2 SPRUFB3 – September 2007 Submit Documentation Feedback...
Page 3: Table Of Contents
Contents ..........................Preface ......................Introduction ......................Device Overview ......................Block Diagram ..................ARM Subsystem in DM355 ..................ARM Subsystem Overview .................. Purpose of the ARM Subsystem ................Components of the ARM Subsystem ....................... References ........................ ARM Core ......................Introduction ..................... Operating States/Modes ..................
Page 4 ..................6.4.1 Multipliers and Dividers ....................6.4.2 Bypass Mode ......................6.4.3 PLL Mode ..................... PLL Configuration ................. 6.5.1 PLL Mode and Bypass Mode ................6.5.2 Changing Divider / Multiplier Ratios ................6.5.3 PLL Power Down and Wakeup ..................PLL Controller Register Map ......................
Page 5 ..............7.7.7 Power Error Pending Register (PERRPR) ..............7.7.8 Power Error Clear Register (PERRCR) ............7.7.9 External Power Control Pending Register (EPCPR) ............7.7.10 External Power Control Clear Register (EPCCR) ..........7.7.11 Power Domain Transition Command Register (PTCMD) ............ 7.7.12 Power Domain Transition Status Register (PTSTAT) .............
Page 6 ..................... 9.5.2 USB PHY Control ..............9.5.3 VPSS Clock and DAC Control and Status ................ 9.5.4 DDR I/O Timing Control and Status ................. Clock Out Configuration Status .................... GIO De-Bounce Control ....................Power Managment ................... 9.8.1 Deep Sleep Control ................... Bandwidth Management ................
Page 7 ......................Boot Modes ....................11.1 Boot Modes Overview ....................... 11.1.1 Features ................... 11.1.2 Functional Block Diagram ..................... 11.2 ARM ROM Boot Modes .................... 11.2.1 NAND Boot Mode ..................11.2.2 MMC/SD Boot Mode .................... 11.2.3 UART Boot Mode ....................Power Management ........................
Page 8 List of Figures ..................DM355 Functional Block Diagram ................DM355 ARM Subsystem Block Diagram ..................... DM355 Clocking Architecture ..................PLLC1 Configuration in DM355 ..................PLLC2 Configuration in DM355 ............... Clock Ratio Change and Alignment with Go Operation ....................Peripheral ID Register (PID) ..................
Page 9 ..................8-12 Interrupt Enable Register 1 (EINT1) ............... 8-13 Interrupt Operation Control Register (INTCTL) ........................8-14 EABASE ................. 8-15 Interrupt Priority Register 0 (INTPRI0) ................. 8-16 Interrupt Priority Register 1 (INTPRI1) ................. 8-17 Interrupt Priority Register 2 (INTPRI2) ................. 8-18 Interrupt Priority Register 3 (INTPRI3) .................
Page 10 List of Tables ..................Exception Vector Table for ARM ................Different Address Types in ARM System ....................ITCM/DTCM Memory Map ....................ITCM/DTCM Size Encoding ..................... ETM Part Descriptions ...................... DM355 Memory Map ............... DM355 ARM Configuration Bus Access to Peripherals ......................
Page 11 ..................... AINTC Interrupt Connections ..................Interrupt Controller (INTC) Registers ..........Interrupt Status of INT[31:0] (if mapped to FIQ) Field Descriptions ..........Interrupt Status of INT[63:32] (if mapped to FIQ) Field Descriptions ..........Interrupt Status of INT[31:0] (if mapped to IRQ) Field Descriptions ..........
Page 12 ................ 11-5 MMC/SD UBL Signatures and Special Modes ....................11-6 UART Data Sequences ....................11-7 Host Utility Data Format ....................11-8 CRC32 Table Transfer ................... 12-1 Power Management Features List of Tables SPRUFB3 – September 2007 Submit Documentation Feedback...
Page 13: Preface
Preface SPRUFB3 – September 2007 Read This First About This Manual Describes the operation of the ARM subsystem in the TMS320DM355 Digital Media System-on-Chip (DMSoC). Notational Conventions This document uses the following conventions. • Hexadecimal numbers are shown with the suffix h. For example, the following number is 40 hexadecimal (decimal 64): 40h.
Page 14 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRUED4— TMS320DM35x DMSoC Serial Peripheral Interface (SPI) Reference Guide This document describes the serial peripheral interface (SPI) in the TMS320DM35x Digital Media System-on-Chip (DMSoC). The SPI is a high-speed synchronous serial input/output port that allows a serial bit stream of programmed length (1 to 16 bits) to be shifted into and out of the device at a programmed bit-transfer rate.
Page 15 (DMSoC). SPRUFC8— TMS320DM355 DMSoC Peripherals Overview Reference Guide This document provides an overview of the peripherals in the TMS320DM355 Digital Media System-on-Chip (DMSoC). The following documents describe TMS320DM35x Digital Media System-on-Chip (DMSoC) that are not available by literature number. Copies of these documents are available (by title only) on the internet at www.ti.com.
Page 16: Introduction
SPRUFB3 – September 2007 Introduction Device Overview DM355 is a highly integrated, programmable Digital Media System-on-Chip (DMSoC) platform for digital still camera and mobile systems that require digital media encode and decode capabilities. Designed to offer end-equipment manufacturers the ability to produce affordable DSC products with high picture quality, DM355 combines programmable image processing capability with a highly integrated set of imaging peripherals.
Page 17: Arm Subsystem In Dm355
www.ti.com ARM Subsystem in DM355 The detailed DM355 block diagram is shown in Figure 1-1. Figure 1-1. DM355 Functional Block Diagram CCD/ CCDC IPIP IPIPE CMOS Module LD/CM LD / Enhanced VPFE Enhanced DMA DLL/ 16 bit DDR2/MDDR 16 64 channels channels controller 3PCC /TC...
Page 18: Arm Subsystem Overview
SPRUFB3 – September 2007 ARM Subsystem Overview Purpose of the ARM Subsystem The ARM Subsystem contains components required to provide the ARM926EJ-S (ARM) master control of the overall DM355 system, including control over the VPSS Subsystem, the peripherals, and external memories.
Page 19: References
www.ti.com References • Video Processing Front End (VPFE) – CCD Controller (CCDC) – Image Pipe (IPIPE) – H3A Engine (Hardware engine for computing Auto-focus, Auto white balance, and Auto exposure) – Multiply Mask / Lens Distortion Module (CFALD) • Video Processing Back End (VPBE) –...
Page 20: Arm Core
SPRUFB3 – September 2007 ARM Core Introduction This chapter describes the ARM core and its associated memories. The ARM core consists of the following components: • ARM926EJ-S - 32-bit RISC processor • 16-KB Instruction cache • 8-KB Data cache • MMU •...
Page 21: Operating States/Modes
www.ti.com Operating States/Modes Operating States/Modes The ARM can operate in two states: ARM (32-bit) mode and Thumb (16-bit) mode. You can switch the ARM926EJ-S processor between ARM mode and Thumb mode using the BX instruction. The ARM can operate in the following modes: •...
Page 22: Exceptions And Exception Vectors
www.ti.com Exceptions and Exception Vectors Exceptions and Exception Vectors Exceptions arise when the normal flow of the program must be temporarily halted. The exceptions that occur in an ARM system are given below: • Reset exception: processor reset • FIQ interrupt: fast interrupt •...
Page 23: Coprocessor 15 (Cp15)
www.ti.com Coprocessor 15 (CP15) a 16-bit architecture is its ability to manipulate 32-bit integers with single instructions, and to address a large address space efficiently. When processing 32-bit data, a 16-bit architecture takes at least two instructions to perform the same task as a single 32-bit instruction. However, not all of the code in a program processes 32-bit data (e.g., code that performs character string handling), and some instructions (like branches) do not process any data at all.
Page 24: Memory Management Unit
www.ti.com Coprocessor 15 (CP15) 3.6.2 Memory Management Unit The ARM926EJ-S MMU provides virtual memory features required by operating systems such as SymbianOS, WindowsCE, and Linux. A single set of two level page tables stored in main memory controls the address translation, permission checks, and memory region attributes for both data and instruction accesses.
Page 25: Caches And Write Buffer
www.ti.com Coprocessor 15 (CP15) 3.6.3 Caches and Write Buffer The ARM926EJ-S processor includes: • An Instruction cache (Icache) • A Data cache (Dcache) • A write buffer The size of the data cache is 8KB, instruction cache is 16KB, and write buffer is 17 bytes. The caches have the following features: •...
Page 26: Tightly Coupled Memory
www.ti.com Tightly Coupled Memory Tightly Coupled Memory The ARM926EJ-Shas a tightly coupled memory interface enabling separate instruction and data TCM to be interfaced to the ARM. TCMs are meant for storing real-time and performance critical code. DM355 supports both instruction TCM (I-TCM) and data TCM (D-TCM). The instruction TCM is located at 0x0000:0000 to 0x0000:7FFF.
Page 27: Embedded Trace Support
www.ti.com Embedded Trace Support Write 0 to the ENB bit to enable ITCM and DTCM. Write 1 to the ENB bit to enable it. The physical address of the memory should be set to the ADDRESS field. The SIZE field reflects the size. The size encoding is given below in Table 3-4.
Page 28 www.ti.com Embedded Trace Support The ETM is used to compress the trace information and export it through a narrow trace port. An external Trace Port Analyzer (TPA) is used to capture the trace information. Note: Chapter 10 of the Embedded Trace Macro-cell Support of the ARM926EJ-S TRM, downloadable from http://www.arm.com for more detailed information.
Page 29: Memory Mapping
SPRUFB3 – September 2007 Memory Mapping Memory Map The DM355 memory map is shown in Table 4-1. The multiple columns represent the memory map of each of the masters on the chip. The ARM, EDMA, USB, and VPSS are all masters with access to the regions shown in the table.
Page 30: Arm Internal Memories
www.ti.com Memory Map 4.1.1 ARM Internal Memories The ARM has access to the following ARM internal memories: • 32KB ARM Internal RAM on TCM interface, logically separated into two 16KB pages to allow simultaneous access on any given cycle, if there are separate accesses for code (I-TCM bus) and data (D-TCM) to the different memory regions.
Page 31: Mpeg/Jpeg Coprocessor (Mjcp)
www.ti.com Memory Map 4.1.3 MPEG/JPEG Coprocessor (MJCP) DM355 performance is enhanced by its dedicated hard-wired MPEG/JPEG coprocessor (MJCP). The MJCP performs all the computational operations required for JPE and MPEG4 compression. These operations can be invoked using the xDM (xDIAS for Digital Media) APIs. For more information, refer to the xDIAS-DM (xDIAS for Digital Media) User's Guide (SPRUEC8).
Page 32 www.ti.com Memory Map Table 4-2. DM355 ARM Configuration Bus Access to Peripherals (continued) Address Accessibility √ √ PWM3 0x01C2 2C00 0x01C2 2FFF √ √ System Module 0x01C4 0000 0x01C4 07FF √ √ PLL Controller 0 0x01C4 0800 0x01C4 0BFF √ √...
Page 33: Memory Interfaces Overview
www.ti.com Memory Interfaces Overview Memory Interfaces Overview This section describes the different memory interfaces of DM355. DM355 supports several memory and external device interfaces, including the following: • DDR2 / mDDR Synchronous DRAM • Asynchronous EMIF • NAND Flash • OneNAND flash 4.2.1 DDR2 EMIF The DDR2 EMIF interface, sometimes referred to as EMIF3.0 in DM355 documentation, is a dedicated interface to DDR and MDDR SDRAM.
Page 34 www.ti.com Memory Interfaces Overview 4.2.2.2 NAND (NAND, SmartMedia, xD) The NAND mode supports the following features: • NAND Flash on up to two asynchronous chip selects • Supports 8-bit and 16-bit data bus widths • Programmable cycle timings • Performs 1-bit and 4-bit ECC calculation (does not perform error correction) •...
Page 35: Device Clocking
SPRUFB3 – September 2007 Device Clocking Overview The DM355 requires one primary reference clock . The reference clock frequency may be generated either by crystal input or by external oscillator. The reference clock is the clock at the pins named MXI1/MXOI.
Page 36: Peripheral Clocking Considerations
www.ti.com Peripheral Clocking Considerations Figure 5-1. DM355 Clocking Architecture SYSCLKBP CLKOUT2 BPDIV (/3) Reference clock AUXCLK (MXI/MXO) UART0, 1 AUXCLK (/1) 24 MHz or 36 Mhz SYSCLK1 PLLDIV1 (/2) ARM subsystem MPEG/JPEG PWMs (x4) Coprocessor Timers (x4) CLKOUT1 Reference clock SYSCLK2 (MXI/MXO) PLLDIV2 (/4)
Page 37: Video Processing Back End Clocking
• PLL1 SYSCLK3 • EXTCLK pin (external VPBE clock input pin) • PCLK pin (VPFE pixel clock input pin) See the TMS320DM355 DMSoC Video Processing Back End (VPBE) Reference Guide for complete information on VPBE clocking. 5.2.2 USB Clocking The USB Controller is driven by two clocks: an output clock of PLL1 and an output clock of the USB Phy.
Page 38: Pll Controllers (Pllcs)
SPRUFB3 – September 2007 PLL Controllers (PLLCs) PLL Controller Module The DM355 has two PLL controllers that provide clocks to different components of the chip. PLL controller 1 (PLLC1) provides clocks to most of the components of the chip. PLL controller 2 (PLLC2) provides clocks to the DDR PHY.
Page 39: Pllc1
www.ti.com PLLC1 PLLC1 PLLC1 provides most of the DM355 clocks. Software controls PLLC1 operation through the PLLC1 registers. The following list, Table 6-1, and Figure 6-1 describe the customizations of PLLC1 in the DM355. • Provides primary DM355 system clock •...
Page 40: Pllc2
www.ti.com PLLC2 Figure 6-1. PLLC1 Configuration in DM355 CLKMODE PLLEN CLKIN Post-DIV Pre-DIV SYSCLK1 (/2 or /1) (/8) (ARM and MPEG/JPEG OSCIN PLLDIV1 (/2) Coprocessor) SYSCLK2 PLLM PLLDIV2 (/4) (peripherals) (programmable) SYSCLK3 PLLDIV3 (/3) (VPBE) SYSCLK4 PLLDIV4 (/4 or /2) (VPSS) AUXCLK (Peripherals,...
Page 41: Pllc Functional Description
www.ti.com PLLC Functional Description Figure 6-2. PLLC2 Configuration in DM355 CLKMODE PLLEN CLKIN Post-DIV Pre-DIV (/1) (programmable) SYSCLK1 OSCIN PLLDIV1 (/1) (DDR PHY) PLLM (programmable) SYSCLKBP BPDIV (/8) (CLKOUT3) PLLC Functional Description This section describes the multiplier and dividers in the PLL controller as well as the bypass and PLL modes of operation.
Page 42: Pll Configuration
www.ti.com PLL Configuration PLL Configuration This section describes the procedures for initializing and configuring the PLL controller. 6.5.1 PLL Mode and Bypass Mode 6.5.1.1 PLL Mode (PLLEN = 1) This section describes the sequence for PLL mode. 1. In PLLCTL, write CLKMODE = 0 (internal oscillator) or 1 (input clock) to select the type of reference clock.
Page 43: Clock Ratio Change And Alignment With Go Operation
www.ti.com PLL Configuration 6.5.2.1.1 GO Operation Writes to the RATIO field in the PLLDIVn registers do not change the dividers’ actual divide ratios immediately. The PLLDIVn dividers only change to the new RATIO rates during a GO operation. This section discusses the GO operation and how the SYSCLKs are aligned. The PLL controller clock align control register (ALNCTL) determines which SYSCLKs must be aligned.
Page 44: Pll Power Down And Wakeup
www.ti.com PLL Controller Register Map 6.5.2.2 Pre-Divider (PREDIV), PLL Multiplier (PLLM), and Post-Divider (POSTDIV) To change the values of PREDIV, PLLM, or POSTDIV; the PLL controller must first be placed in bypass mode. Perform the following steps to modify PREDIV, PLLM, or POSTDIV ratios. 1.
Page 45 www.ti.com PLL Controller Register Map Table 6-4. PLLC Registers (continued) Offset Acronym Register Description Section 138h PLLCMD PLL controller command register Section 6.6.11 13Ch PLLSTAT PLL controller status register Section 6.6.12 140h ALNCTL SYSCLKn divider ratio change and align control register Section 6.6.13 144h DCHANGE...
Page 46: Peripheral Id Register (Pid)
www.ti.com PLL Controller Register Map 6.6.2 Peripheral ID Register (PID) The peripheral ID register (PID) is shown in Figure 6-4 and described in Table 6-5 for PLLC1 and PLLC2. Note that bit field descriptions shown in Figure 6-4 are given for PLLC1 (top) and PLLC2 (bottom). This format is used in the bit description figures throughout this section.
Page 47: Pll Control (Pllctl)
www.ti.com PLL Controller Register Map 6.6.3 PLL Control (PLLCTL) The PLL control register is shown in Figure 6-5 and described in Table 6-6 for PLLC1 and PLLC2. Figure 6-5. PLL Control Register (PLLCTL) Reserved Reserved CLKMODE R/W-0 R/W-0 Reserved PLLENSRC PLLDIS PLLRST Reserved...
Page 48: Pll Multiplier Control Register (Pllm)
www.ti.com PLL Controller Register Map 6.6.4 PLL Multiplier Control Register (PLLM) The PLL multiplier control register (PLLM) is shown in Figure 6-6 and described in Table 6-7 for PLLC1 and PLLC2. For PLLC1, the default multiplier value is 180. For PLLC2, the default multiplier value is 92. You may change the multiplier value from 92 to 184.
Page 49: Pll Pre-Divider Control Register (Prediv)
www.ti.com PLL Controller Register Map 6.6.5 PLL Pre-Divider Control Register (PREDIV) The PLL pre-divider control register (PREDIV) is shown in Figure 6-7 and described in Table 6-8 PLLC1 and PLLC2. For PLLC1, the pre-divider ratio is fixed (cannot be changed) to 8. For PLLC2, the pre-divider ratio defaults to 8, however, it may be changed to allow for lower frequencies.
Page 50: Pll Controller Divider 1 Register (Plldiv1)
www.ti.com PLL Controller Register Map 6.6.6 PLL Controller Divider 1 Register (PLLDIV1) The PLL controller divider 1 register (PLLDIV1) is shown in Figure 6-8 and described in Table 6-9 PLLC1 and PLLC2. PLLDIV1 controls the divider for SYSCLK1. The divider for PLLC1 SYSCLK1 is fixed (cannot be changed) to (/2).
Page 51: Pll Controller Divider 2 Register (Plldiv2)
www.ti.com PLL Controller Register Map 6.6.7 PLL Controller Divider 2 Register (PLLDIV2) The PLL controller divider 2 register (PLLDIV2) is shown in Figure 6-9 and described in Table 6-10 PLLC1 and PLLC2. PLLDIV2 controls the divider for SYSCLK2. The divider for PLLC1 SYSCLK2 is fixed (cannot be changed) to (/4).
Page 52: Pll Controller Divider 3 Register (Plldiv3)
www.ti.com PLL Controller Register Map 6.6.8 PLL Controller Divider 3 Register (PLLDIV3) The PLL controller divider 3 register (PLLDIV3) is shown in Figure 6-10 and described in Table 6-11 PLLC1 and PLLC2. PLLDIV3 controls the divider for SYSCLK3. The divider for PLLC1 SYSCLK3 is programmable.
Page 53: Pll Post-Divider Control Register (Postdiv)
www.ti.com PLL Controller Register Map 6.6.9 PLL Post-Divider Control Register (POSTDIV) The PLL post-divider control register (POSTDIV) is shown in Figure 6-11 and described in Table 6-12 PLLC1 and PLLC2. POSTDIV is a read only register. The post divider ratio for PLLC1 may be changed by the bit PLL1_POSTDIV in the miscellaneous control register (MISC) in the System Control module.
Page 54: Bypass Divider Register (Bpdiv)
www.ti.com PLL Controller Register Map 6.6.10 Bypass Divider Register (BPDIV) The bypass divider register (BPDIV) is shown in Figure 6-12 and described in Table 6-13 for PLLC1 and PLLC2. BPDIV controls the divider for SYSCLKBP. The divider for PLLC1 SYSCLKBP is fixed (cannot be changed) to 3.
Page 55: Pll Controller Command Register (Pllcmd)
www.ti.com PLL Controller Register Map 6.6.11 PLL Controller Command Register (PLLCMD) The PLL controller command register (PLLCMD) is shown in Figure 6-13 and described in Table 6-14 PLLC1 and PLLC2. PLLCMD is used to initiate a GO operation for SYSCLKn ratio change and/or phase alignment.
Page 56: Pll Controller Status Register (Pllstat)
www.ti.com PLL Controller Register Map 6.6.12 PLL Controller Status Register (PLLSTAT) The PLL controller status register (PLLSTAT) is shown in Figure 6-14 and described in Table 6-15 PLLC1 and PLLC2. PLLSTAT shows the status of changing SYSCLKn divider ratios and/or phase alignment.
Page 57: Pll Controller Clock Align Control Register (Alnctl)
www.ti.com PLL Controller Register Map 6.6.13 PLL Controller Clock Align Control Register (ALNCTL) The PLL controller clock align control register (ALNCTL) is shown in Figure 6-15 and described in Table 6-16 for PLLC1 and PLLC2. ALNCTL controls SYSCLK divider ratio change and alignment when GOSET bit in PLLCMD is set to 1.
Page 58: Plldiv Ratio Change Status Register (Dchange)
www.ti.com PLL Controller Register Map 6.6.14 PLLDIV Ratio Change Status Register (DCHANGE) The PLLDIV ratio change status register (DCHANGE) is shown in Figure 6-16 and described in Table 6-17 for PLLC1 and PLLC2. Whenever a different ratio is written to the PLLDIVn registers, the PLLC flags the change in DCHANGE.
Page 59: Clock Enable Control Register (Cken)
www.ti.com PLL Controller Register Map 6.6.15 Clock Enable Control Register (CKEN) The clock enable control register (CKEN) is shown in Figure 6-17 and described in Table 6-18 for PLLC1 and PLLC2. The CKEN register is used to enable the PLL auxiliary clock (AUXCLK). The auxiliary clock should always be enabled, so you must always set this bit to 1.
Page 60: Clock Status Register (Ckstat)
www.ti.com PLL Controller Register Map 6.6.16 Clock Status Register (CKSTAT) The clock status (CKSTAT) register is shown in Figure 6-18 and described in Table 6-19 for PLLC1 and PLLC2. CKSTAT shows the on/off status of the bypass clock (SYSCLKBP) and the auxiliary clock (AUXCLK).
Page 61: Sysclk Status Register (Systat)
www.ti.com PLL Controller Register Map 6.6.17 SYSCLK Status Register (SYSTAT) The SYSCLK status register (SYSTAT) is shown in Figure 6-19 and described in Table 6-20 for PLLC1 and PLLC2. SYSTAT shows the on/off status of the SYSCLKn clocks. Figure 6-19. SYSCLK Status Register (SYSTAT) Reserved Reserved SYSONn...
Page 62: Pll Controller Divider 4 Register (Plldiv4)
www.ti.com PLL Controller Register Map 6.6.18 PLL Controller Divider 4 Register (PLLDIV4) The PLL controller divider 4 register (PLLDIV4) is shown in Figure 6-20 and described in Table 6-21 PLLC1 and PLLC2. PLLDIV4 controls the divider for SYSCLK4. The divider for PLLC1 SYSCLK4 is programmable.
Page 63: Power And Sleep Controller
SPRUFB3 – September 2007 Power and Sleep Controller Introduction In the DM355 system, the Power and Sleep Controller (PSC) is responsible for managing transitions of system power on/off, clock on/off, and reset. A block diagram of the PSC is shown in Figure 7-1.
Page 64: Dm355 Power Domain And Module Topology
www.ti.com DM355 Power Domain and Module Topolgy Figure 7-2. DM355 Power Domain and Module Topology UART 0 UART 1 Timer 0 CLKIN domain Timer 1 PWM 3 Timer 2 Timer 3 PWM 2 PWM 0 PWM 1 CLKDIV 2 domain subsystem MPEG/JPEG Coprocessor...
Page 65: Module Configuration
www.ti.com DM355 Power Domain and Module Topolgy Table 7-1. Module Configuration Default States Module Module Name Power Domain Power Domain State Module State Number VPSS Master AlwaysOn SyncRst VPSS Slave AlwaysOn SyncRst EDMA (CC) AlwaysOn BTSEL[1:0] = 00 – Enable (NAND) BTSEL[1:0] = 01 –...
Page 66: Power Domain And Module States Defined
www.ti.com Power Domain and Module States Defined Table 7-1. Module Configuration (continued) Default States AlwaysOn Enable AlwaysOn Enable AlwaysOn Enable AlwaysOn Enable Emulation AlwaysOn Enable Test AlwaysOn Enable Test AlwaysOn Enable Test AlwaysOn Enable Reserved Reserved Reserved Reserved MPEG/JPEG AlwaysOn SyncRst Coprocessor (MJCP) VPSS DAC...
Page 67: Executing State Transitions
www.ti.com Executing State Transitions The module states are defined as follows: Module State Module State Definition Enable A module in the enable state has its module reset de-asserted and it has its clock on. This is the normal run-time state for a given module. Disable A module in the disable state has its module reset de-asserted and it has its clock off.
Page 68: Psc Interrupts
www.ti.com PSC Interrupts Table 7-3. IcePick Emulation Commands (continued) Power On and Enable Features Power On and Enable Descriptions Reset Features Reset Descriptions Force Power Allows emulation to force the power Wait Reset Allows emulation to keep domain into an on state local reset asserted for an extended period of time after software initiates local...
Page 69: Interrupt Registers
www.ti.com PSC Interrupts 7.6.1.2 Module State Emulation Events A module state emulation event occurs when emulation alters the state of a module. Status is reflected in the EMUIHB bit in the MDSTAT[x]. In particular, a module state emulation event occurs under the following conditions: •...
Page 70 www.ti.com PSC Interrupts 1. Set the EMUIHB bit in PDCTLx, the EMUIHB bit in MDCTL[x], and / or the EMURSTIE bit in MDCTL[x] to enable the interrupt events that you want. Note: There is no enable bit for the external power control pending interrupt event, so effectively this event is always enabled.
Page 71: Psc Registers
www.ti.com PSC Registers The ARM enters the interrupt service routine (ISR) when it receives the interrupt. 1. Read the Px bit in PERRPR, the Mx bit in MERRPR0, the Mx bit in MERRPR1, and / or the EP bit in EPCPR to determine the source of the interrupt(s).
Page 72: Peripheral Revision And Class Information (Pid)
www.ti.com PSC Registers 7.7.1 Peripheral Revision and Class Information (PID) The peripheral revision and class information (PID) register is shown in Figure 7-3 and described in Table 7-6. Figure 7-3. Peripheral Revision and Class Information Register (PID) SCHEME Reserved FUNC R- 1 R- 208 MAJOR...
Page 73: Interrupt Evaluation Register (Inteval)
www.ti.com PSC Registers 7.7.2 Interrupt Evaluation Register (INTEVAL) The interrupt evaluation register (INTEVAL) is shown in Figure 7-4 and described in Table 7-7. Figure 7-4. Interrupt Evaluation Register (INTEVAL) Reserved Reserved Reserved ALLEV LEGEND: R = Read only; -n = value after reset Table 7-7.
Page 74: Module Error Pending Register 0 (Mod 0 - 31) (Merrpr0)
www.ti.com PSC Registers 7.7.3 Module Error Pending Register 0 (mod 0 - 31) (MERRPR0) The module error pending register 0 (mod 0 - 31) is shown in Figure 7-5 and described in Table 7-8. Figure 7-5. Module Error Pending Register 0 (mod 0 - 31) (MERRPR0) M0[32] R- 0 LEGEND: R = Read only;...
Page 75: Module Error Pending Register 1 (Mod 32 - 41) (Merrpr1)
www.ti.com PSC Registers 7.7.4 Module Error Pending Register 1 (mod 32 - 41) (MERRPR1) The module error pending register 1 (mod 32 - 41) (MERRPR1) is shown in Figure 7-6 and described in Table 7-9. Figure 7-6. Module Error Pending Register 1 (mod 32 - 41) (MERRPR1) Reserved Reserved M[9]...
Page 76: Module Error Clear Register 0 (Mod 0-31) (Merrcr0)
www.ti.com PSC Registers 7.7.5 Module Error Clear Register 0 (mod 0-31) (MERRCR0) The module error clear 0 (mod 0-31) register (MERRCR0) is shown in Figure 7-7 and described in Table 7-10. Figure 7-7. Module Error Clear Register 0 (mod 0-31) (MERRCR0) M[32] R- 0 LEGEND: R = Read only;...
Page 77: Module Error Clear Register 1 (Mod 32-41) (Merrcr1)
www.ti.com PSC Registers 7.7.6 Module Error Clear Register 1 (mod 32-41) (MERRCR1) The module error clear 1 (mod 32-63) register (MERRCR1) is shown in Figure 7-8 and described in Table 7-11. Figure 7-8. Module Error Clear Register 1 (mod 32-41) (MERRCR1) Reserved Reserved M[9]...
Page 78: Power Error Pending Register (Perrpr)
www.ti.com PSC Registers 7.7.7 Power Error Pending Register (PERRPR) The power error pending register (PERRPR) is shown in Figure 7-9 and described in Table 7-12. Figure 7-9. Power Error Pending Register (PERRPR) Reserved Reserved P[1] LEGEND: R = Read only; -n = value after reset Table 7-12.
Page 79: Power Error Clear Register (Perrcr)
www.ti.com PSC Registers 7.7.8 Power Error Clear Register (PERRCR) The power error clear register (PERRCR) is shown in Figure 7-10 and described in Table 7-13. Figure 7-10. Power Error Clear Register (PERRCR) Reserved Reserved P[1] LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7-13.
Page 80: External Power Control Pending Register (Epcpr)
www.ti.com PSC Registers 7.7.9 External Power Control Pending Register (EPCPR) The external power control pending register (EPCPR) is shown in Figure 7-11 and described in Table 7-14. Figure 7-11. External Power Control Pending Register (EPCPR) Reserved Reserved EPC[1] LEGEND: R = Read only; -n = value after reset Table 7-14.
Page 81: External Power Control Clear Register (Epccr)
www.ti.com PSC Registers 7.7.10 External Power Control Clear Register (EPCCR) The external power control clear register (EPCCR) is shown in Figure 7-12 and described in Table 7-15. Figure 7-12. External Power Control Clear Register (EPCCR) Reserved Reserved EPC[1] LEGEND: R = Read only; -n = value after reset Table 7-15.
Page 82: Power Domain Transition Command Register (Ptcmd)
www.ti.com PSC Registers 7.7.11 Power Domain Transition Command Register (PTCMD) The power domain transition command register (PTCMD) is shown in Figure 7-13 and described in Table 7-16. Figure 7-13. Power Domain Transition Command Register (PTCMD) Reserved Reserved GO[1] LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7-16.
Page 83: Power Domain Transition Status Register (Ptstat)
www.ti.com PSC Registers 7.7.12 Power Domain Transition Status Register (PTSTAT) The power domain transition status register (PTSTAT) is shown in Figure 7-14 and described in Table 7-17 Figure 7-14. Power Domain Transition Status Register (PTSTAT) Reserved Reserved GOSTAT[1] LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7-17.
Page 84: Power Domain Status Register 0 (Pdstatn)
www.ti.com PSC Registers 7.7.13 Power Domain Status Register 0 (PDSTATn) The power domain status n register (PDSTATn) is shown in Figure 7-15 and described in Table 7-18. Figure 7-15. Power Domain Status n Register (PDSTATn) Reserved Reserved EMUIHB Reserved PORDONE Reserved STATE LEGEND: R = Read only;...
Page 85: Power Domain Control N Register 0 (Pdctln)
www.ti.com PSC Registers 7.7.14 Power Domain Control n Register 0 (PDCTLn) The power domain control n register (PDCTLn) is shown in Figure 7-16 and described in Table 7-19. In DM355 only PDCTL0 is applicable because there is only one power domain, the AlwaysOn power domain. The AlwaysOn power domain is always on when voltage is applied to the DM355;...
Page 86: Module Status N Register 0-41 (Mdstatn)
www.ti.com PSC Registers 7.7.15 Module Status n Register 0-41 (MDSTATn) The module status 0 register (MDSTATn) is shown in Figure 7-17 and described in Table 7-20. See Table 7-1 for after reset default module states. Figure 7-17. Module Status n Register (MDSTATn) Reserved EMUIHB EMURST...
Page 87: Module Control N Register 0-41 (Mdctln)
www.ti.com PSC Registers 7.7.16 Module Control n Register 0-41 (MDCTLn) The module control n register 0-41 (MDCTLn) is shown in Figure 7-18 and described in Table 7-21. See Table 7-1 for after reset default module states. It is not possible to change the module states for modules 29 through 38.
Page 88: Interrupt Controller
SPRUFB3 – September 2007 Interrupt Controller Introduction The DM355 ARM Interrupt Controller (AINTC) has the following features: • Supports up to 64 interrupt channels (16 external channels) • Interrupt mask for each channel • Each interrupt channel is mappable to a Fast Interrupt Request (FIQ) or to an Interrupt Request (IRQ) type of interrupt.
Page 89: Intc Methodology
www.ti.com INTC Methodology Table 8-1. AINTC Interrupt Connections (continued) Interrupt Acronym Source Interrupt Acronym Source Number Number VPSSINT5 VPSS - INT5 PWMINT1 PWM 1 VPSSINT6 VPSS - INT6 PWMINT2 PWM2 VPSSINT7 VPSS - INT7 I2CINT VPSSINT8 VPSS - INT8 UARTINT0 UART0 UARTINT1 UART1...
Page 90: Interrupt Mapping
www.ti.com INTC Methodology or FIQ interrupt). The ARM then branches to the IRQ or FIQ interrupt routine. • The INTC generates the entry address of the pending interrupt with the highest priority and stores the entry address in the FIQENTRY or the IRQENTRY register, depending on whether the interrupt is mapped to IRQ or FIQ interrupt.
Page 91: Vector Table Entry Address Generation
www.ti.com INTC Methodology 8.3.3 Vector Table Entry Address Generation To help speed up the ISR, the AINTC provides two vectors into the ARM’s interrupt entry table, which correspond to the highest priority effective IRQ and FIQ interrupts. This vector is generated by modifying a base address with a priority index.
Page 92: Enabling And Disabling Interrupts
www.ti.com INTC Methodology 8.3.5 Enabling and Disabling Interrupts The AINTC has two methods for enabling and disabling interrupts: immediate or delayed, based on the setting of the IDMODE bit in the INTCTL register. When 0 (default), clearing an interrupt's EINT bit has an immediate effect.
Page 93: Intc Registers
www.ti.com INTC Registers INTC Registers Table 8-2 lists the memory-mapped registers for the INTC. See the device memory mapTable 4-2 for the memory address of these registers. Table 8-2. Interrupt Controller (INTC) Registers Offset Acronym Register Description Section FIQ0 Interrupt Status of INT [31:0] (if mapped to FIQ) Section 8.4.1 FIQ1 Interrupt Status of INT [63:32] (if mapped to FIQ)
Page 94: Fast Interrupt Request Status Register 0 (Fiq0)
www.ti.com INTC Registers 8.4.1 Fast Interrupt Request Status Register 0 (FIQ0) The fast interrupt request status register 0 (FIQ0) is shown in Figure 8-5 and described in Table 8-3. Figure 8-5. Interrupt Status of INT[31:0] (if mapped to FIQ) FIQ[31:0] R/W-1 FIQ[31:0] R/W-1...
Page 95: Fast Interrupt Request Status Register 1 (Fiq1)
www.ti.com INTC Registers 8.4.2 Fast Interrupt Request Status Register 1 (FIQ1) The fast interrupt request status register 1 (FIQ1) is shown in Figure 8-6 and described in Table 8-4. Figure 8-6. Interrupt Status of INT[63:32] (if mapped to FIQ) FIQ[63:32] FIQ[63:31] R/W-1 LEGEND: R/W = Read/Write;...
Page 96: Interrupt Request Status Register 0 (Irq0)
www.ti.com INTC Registers 8.4.3 Interrupt Request Status Register 0 (IRQ0) The interrupt request status register 0 (IRQ0) is shown in Figure 8-7 and described in Table 8-5. Figure 8-7. Interrupt Status of INT[31:0] (if mapped to IRQ) IRQ[31:0] R/W-1 IRQ[31:0] R/W-1 LEGEND: R/W = Read/Write;...
Page 97: Interrupt Request Status Register 1 (Irq1)
www.ti.com INTC Registers 8.4.4 Interrupt Request Status Register 1 (IRQ1) The interrupt request status register 1 (IRQ1) is shown in Figure 8-8 and described in Table 8-6. Figure 8-8. Interrupt Status of INT[31:0] (if mapped to IRQ) IRQ[63:32] R/W-1 IRQ [63:32] R/W-1 LEGEND: R/W = Read/Write;...
Page 98: Fast Interrupt Request Entry Address Register (Fiqentry)
www.ti.com INTC Registers 8.4.5 Fast Interrupt Request Entry Address Register (FIQENTRY) The fast interrupt request entry address register (FIQENTRY) is shown in Figure 8-9 and described in Table 8-7. Figure 8-9. Fast Interrupt Request Entry Address Register (FIQENTRY) FIQENTRY FIQENTRY LEGEND: R = Read only;...
Page 99: Interrupt Request Entry Address Register (Irqentry)
www.ti.com INTC Registers 8.4.6 Interrupt Request Entry Address Register (IRQENTRY) The interrupt request entry address register (IRQENTRY) is shown in Figure 8-10 and described in Table 8-8. Figure 8-10. Interrupt Request Entry Address Register (IRQENTRY) IRQENTRY IRQENTRY LEGEND: R = Read only; -n = value after reset Table 8-8.
Page 100: Interrupt Enable Register 0 (Eint0)
www.ti.com INTC Registers 8.4.7 Interrupt Enable Register 0 (EINT0) The interrupt enable register 0 (EINT0) is shown in Figure 8-11 and described in Table 8-9. Figure 8-11. Interrupt Enable Register 0 (EINT0) EINT[31:0] R/W-0 EINT[31:0] R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 8-9.
Page 101: Interrupt Enable Register 1 (Eint1)
www.ti.com INTC Registers 8.4.8 Interrupt Enable Register 1 (EINT1) The interrupt enable register 1 (EINT1) is shown in Figure 8-12 and described in Table 8-10. Figure 8-12. Interrupt Enable Register 1 (EINT1) EINT[63:32] EINT[63:32] R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 8-10.
Page 102: Interrupt Operation Control Register (Intctl)
www.ti.com INTC Registers 8.4.9 Interrupt Operation Control Register (INTCTL) The interrupt operation control register (INTCTL) is shown in Figure 8-13 and described in Table 8-11. Figure 8-13. Interrupt Operation Control Register (INTCTL) Reserved Reserved IDMODE IERAW FERAW R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write;...
Page 103: Eabase
www.ti.com INTC Registers 8.4.10 EABASE The EABASE register is shown in Figure 8-14 and described in Table 8-12. Figure 8-14. EABASE Reserved EABASE R/W-0 EABASE Reserved SIZE R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 8-12.
Page 104: Interrupt Priority Register 0 (Intpri0)
www.ti.com INTC Registers 8.4.11 Interrupt Priority Register 0 (INTPRI0) The interrupt priority register 0 (INTPRI0) is shown in Figure 8-15 and described in Table 8-13. Figure 8-15. Interrupt Priority Register 0 (INTPRI0) Reserved INT7 Reserved INT6 Reserved INT5 Reserved INT4 R/W-7 R/W-7 R/W-7...
Page 105: Interrupt Priority Register 1 (Intpri1)
www.ti.com INTC Registers 8.4.12 Interrupt Priority Register 1 (INTPRI1) The interrupt priority register 1 (INTPRI1) is shown in Figure 8-16 and described in Table 8-14. Figure 8-16. Interrupt Priority Register 1 (INTPRI1) Reserved INT15 Reserved INT14 Reserved INT13 Reserved INT12 R/W-7 R/W-7 R/W-7...
Page 106: Interrupt Priority Register 2 (Intpri2)
www.ti.com INTC Registers 8.4.13 Interrupt Priority Register 2 (INTPRI2) The interrupt priority register 2 (INTPRI2) is shown in Figure 8-17 and described in Table 8-15. Figure 8-17. Interrupt Priority Register 2 (INTPRI2) Reserved INT23 Reserved INT22 Reserved INT21 Reserved INT20 R/W-7 R/W-7 R/W-7...
Page 107: Interrupt Priority Register 3 (Intpri3)
www.ti.com INTC Registers 8.4.14 Interrupt Priority Register 3 (INTPRI3) The interrupt priority register 3 (INTPRI3) is shown in Figure 8-18 and described in Table 8-16. Figure 8-18. Interrupt Priority Register 3 (INTPRI3) Reserved INT31 Reserved INT30 Reserved INT29 Reserved INT28 R/W-7 R/W-7 R/W-7...
Page 108: Interrupt Priority Register 4 (Intpri4)
www.ti.com INTC Registers 8.4.15 Interrupt Priority Register 4 (INTPRI4) The interrupt priority register 4 (INTPRI4) is shown in Figure 8-19 and described in Table 8-17. Figure 8-19. Interrupt Priority Register 4 (INTPRI4) Reserved INT39 Reserved INT38 Reserved INT37 Reserved INT36 R/W-7 R/W-7 R/W-7...
Page 109: Interrupt Priority Register 5 (Intpri5)
www.ti.com INTC Registers 8.4.16 Interrupt Priority Register 5 (INTPRI5) The interrupt priority register 5 (INTPRI5) is shown in Figure 8-20 and described in Table 8-18. Figure 8-20. Interrupt Priority Register 5 (INTPRI5) Reserved INT47 Reserved INT46 Reserved INT45 Reserved INT44 R/W-7 R/W-7 R/W-7...
Page 110: Interrupt Priority Register 6 (Intpri6)
www.ti.com INTC Registers 8.4.17 Interrupt Priority Register 6 (INTPRI6) The interrupt priority register 6 (INTPRI6) is shown in Figure 8-21 and described in Table 8-19. Figure 8-21. Interrupt Priority Register 6 (INTPRI6) Reserved INT55 Reserved INT54 Reserved INT53 Reserved INT52 R/W-7 R/W-7 R/W-7...
Page 111: Interrupt Priority Register 7 (Intpri7)
www.ti.com INTC Registers 8.4.18 Interrupt Priority Register 7 (INTPRI7) The interrupt priority register 7 (INTPRI7) is shown in Figure 8-22 and described in Table 8-20. Figure 8-22. Interrupt Priority Register 7 (INTPRI7) Reserved INT63 Reserved INT62 Reserved INT61 Reserved INT60 R/W-7 R/W-7 R/W-7...
Page 112: System Control Module
SPRUFB3 – September 2007 System Control Module Overview of the System Control Module The DM355’s system control module is a system-level module containing status and top-level control logic required by the device. The system control module consists of a miscellaneous set of status and control registers, accessible the ARM and supporting all of the following system features and operations: •...
Page 113: Device Boot Configuration Status
www.ti.com ARM Interrupt and EDMA Event Multiplexing Control 9.3.1.1 Hardware Controlled Default Pin Multiplexing There are configuration input signals that can set some of the default pin mux and hardware configurations that may be needed for device boot. Use pins AECFG[3:0] to configure the pins of the AEMIF.
Page 114: Usb Phy Control
www.ti.com Clock Out Configuration Status 9.5.2 USB PHY Control The USB_PHY_CTL register controls various features of the USB PHY, as shown in Figure 9-14 Table 9-17. 9.5.3 VPSS Clock and DAC Control and Status Clocks for the video processing subsystem are controlled via the VPSS_CLK_CTRL register. Video DAC configuration is controlled by VDAC.
Page 115: Bandwidth Management
www.ti.com Bandwidth Management Bandwidth Management 9.9.1 Bus Master DMA Priority Control In order to determine allowed connections between masters and slaves, each master request source must have a unique master ID (mstid) associated with it. The master ID for each DM355 master is shown in Table 9-1.
Page 116: Dm355 Default Master Priorities
www.ti.com Bandwidth Management Prioritization within each switched central resource (SCR) is selected to be either fixed or dynamic. Dynamic prioritization is based on an incoming priority signal from each master. On DM355, only the DSP, , and EDMA masters actually generate priority values. For all other masters, the value is programmed in the chip-level MSTRPRI registers.
Page 117: System Control Register Descriptions
www.ti.com System Control Register Descriptions 9.10 System Control Register Descriptions 9.10.1 Introduction Table 9-3 lists the memory-mapped registers for the System Module (SYS). See the device memory map Table 4-2 the memory address of these registers. Table 9-3. System Module (SYS) Registers Offset Acronym Register Description...
Page 118: Pinmux0 - Pin Mux 0 (Video In) Pin Mux Register
www.ti.com System Control Register Descriptions 9.10.2 PINMUX0 - Pin Mux 0 (Video In) Pin Mux Register The PINMUX0 register controls pin multiplexing for the VPFE pins. Figure 9-1. PINMUX0 - Pin Mux 0 (Video In) Pin Mux Register RESERVED RESERVED PCLK CAM_WEN CAM_VD...
Page 119 www.ti.com System Control Register Descriptions Table 9-4. PINMUX0 - Pin Mux 0 (Video In) Pin Mux Register Field Descriptions (continued) Field Value Description CIN_6 Enable the CIN[6] (Video In Pin Mux) GIO[100] CIN[6] SPI[2]_SDO _RESV CIN_7 Enable the CIN[7] (Video In Pin Mux) GIO[101] CIN[7] SPI[2]_SCLK...
Page 120: Pinmux1 - Pin Mux 1 (Video Out) Pin Mux Register
www.ti.com System Control Register Descriptions 9.10.3 PINMUX1 - Pin Mux 1 (Video Out) Pin Mux Register The PINMUX1 register controls pin multiplexing for the VPBE pins. Figure 9-2. PINMUX1 - Pin Mux 1 (Video Out) Pin Mux Register RESERVED VCLK EXTCLK FIELD DLCD...
Page 121 www.ti.com System Control Register Descriptions Table 9-5. PINMUX1 - Pin Mux 1 (Video Out) Pin Mux Register Field Descriptions (continued) Field Value Description COUT_3 Enable COUT[3] (Video Out Pin Mux) GIO[77] COUT[3] PWM2 RTO2 COUT_4 Enable COUT[4] (Video Out Pin Mux) GIO[78] COUT[4] PWM2...
Page 122: Pinmux2 - Pin Mux 2 (Aemif) Pin Mux Register
www.ti.com System Control Register Descriptions 9.10.4 PINMUX2 - Pin Mux 2 (AEMIF) Pin Mux Register The PINMUX2 register controls pin multiplexing for the AEMIF pins. Some of the register fields have default values set by external pins that allow control of the AEMIF configuration to match the boot mode. Figure 9-3.
Page 123 www.ti.com System Control Register Descriptions Table 9-6. PINMUX2 - Pin Mux 2 (AEMIF) Pin Mux Register Field Descriptions (continued) Field Value Description EM_BA0 Enable EM_BA0 (AEMIF Pin Mux) Reset value set by AECFG[2:1] - sets AEMIF address usage for boot OneNAND operation requires PINMUX2[4:1] = AECFG[3:0] = 0010b;...
Page 124: Pinmux3 - Pin Mux 3 (Gio/Misc) Pin Mux Register
www.ti.com System Control Register Descriptions 9.10.5 PINMUX3 - Pin Mux 3 (GIO/Misc) Pin Mux Register The PINMUX3 register controls pin multiplexing for the GIO pins. Figure 9-4. PINMUX3 - Pin Mux 3 (GIO/Misc) Pin Mux Register RESERVED GIO7 GIO8 GIO9 GIO10 GIO11 GIO12 GIO13 GIO14 GIO15 GIO16 GIO17 GIO18 R/W-0 R/W-0...
Page 125 www.ti.com System Control Register Descriptions Table 9-7. PINMUX3 - Pin Mux 3 (GIO/Misc) Pin Mux Register Field Descriptions (continued) Field Value Description GIO17 Enable GIO[17] (GPIO Pin Mux) GIO[17] CLKOUT2 GIO18 Enable GIO[18] (GPIO Pin Mux) GIO[18] CLKOUT1 15-14 GIO19 Enable GIO[19] (GPIO Pin Mux) GIO[19] SD1_DATA0...
Page 126: Pinmux3 - Pin Mux 3 (Gio/Misc) Pin Mux Register
www.ti.com System Control Register Descriptions Table 9-7. PINMUX3 - Pin Mux 3 (GIO/Misc) Pin Mux Register Field Descriptions (continued) Field Value Description GIO30 Enable GIO[30] (GPIO Pin Mux) GIO[30] ASP0_BDX System Control Module SPRUFB3 – September 2007 Submit Documentation Feedback...
Page 127: Pinmux4 - Pin Mux 4 (Misc) Pin Mux Register
www.ti.com System Control Register Descriptions 9.10.6 PINMUX4 - Pin Mux 4 (Misc) Pin Mux Register The PINMUX4 register controls pin multiplexing for SPI0 and MMC/SD0. Figure 9-5. PINMUX4 - Pin Mux 4 (Misc) Pin Mux Register RESERVED RESERVED RESERVED MMCSD0_MS SPIO_SDI SPI0_SDENA R/W-0...
Page 128: Bootcfg - Boot Configuration
www.ti.com System Control Register Descriptions 9.10.7 BOOTCFG - Boot Configuration The device boot configuration (the state of the BTSEL[1:0] and AECFG[3:0] signals are captured in the BOOTCFG register). Figure 9-6. BOOTCFG - Boot Configuration RESERVED RESERVED GIO0_RESET BTSEL RESERVED AECFG R-1101 LEGEND: R/W = Read/Write;...
Page 129: Arm_Intmux - Arm Interrupt Mux Control Register
www.ti.com System Control Register Descriptions 9.10.8 ARM_INTMUX - ARM Interrupt Mux Control Register The ARM_INTMUX register provides multiplexing control for interrupts to the ARM since the Interrupt Controller (INTC) can only support 64 discrete events. Figure 9-7. ARM_INTMUX - ARM Interrupt Mux Control Register RESERVED RESERVED INT20...
Page 130: Edma_Evtmux - Edma Event Mux Control Register
www.ti.com System Control Register Descriptions 9.10.9 EDMA_EVTMUX - EDMA Event Mux Control Register The EDMA_EVTMUX register controls multiplexing for EDMA Events due to the limited number of events supported by the EDMA. Figure 9-8. EDMA_EVTMUX - EDMA Event Mux Control Register RESERVED RESERVED EVT26...
Page 131: Ddr_Slew - Ddr Slew
www.ti.com System Control Register Descriptions 9.10.10 DDR_SLEW - DDR Slew The DDR_SLEW registers allows firmware control of the DDR Slew Rate. Figure 9-9. DDR_SLEW - DDR Slew RESERVED RESERVED DDRDATA_ DDRCMD_ SLEW SLEW LEGEND: R = Read only; -n = value after reset Table 9-12.
Page 132: Clkout - Clkout Divisor / Output Control
www.ti.com System Control Register Descriptions 9.10.11 CLKOUT - CLKOUT Divisor / Output Control The CLKOUT register provides control of divisors and output enables for CLKOUT[3:1]. In DM355, this register is read only. The CLKOUT[3:1] pins are multiplexed. Use the PINMUX3 register in the system control module to control the pin multiplexing for CLKOUT[3:1].
Page 133: Device_Id - Device Id
[26:24] - Capability = 111: ARM Processor with J extension - soft macrocell [23:20] - Family = 1001: 0x9 [19:12] - Device Number = 0010 0110: 0x26 11-1 MFGR Manufacturer's JTAG ID Texas Instruments' Mfg ID RESERVED Reserved (Always 1) SPRUFB3 – September 2007 System Control Module...
Page 134: Vdac_Config - Video Dac Configuration
www.ti.com System Control Register Descriptions 9.10.13 VDAC_CONFIG - Video Dac Configuration the VDAC_CONFIG register provides control of the Video DAC. Figure 9-12. VDAC_CONFIG - Video Dac Configuration RESERVED TRESB4R4 TRESB4R2 TRESB4R1 TRIMBITS R/W-0xC R/W-0x8 R/W-0xC R/W-0x37 TRIMBITS PWD_BGZ SPEED TVINT R/W-0x37 R/W-0 R/W-1...
Page 135: Timer64_Ctl - Timer64+ Input Control
www.ti.com System Control Register Descriptions 9.10.14 TIMER64_CTL - Timer64+ Input Control The TIMER64_CTL register provides Timer64+ input control. Figure 9-13. TIMER64_CTL - Timer64+ Input Control RESERVED RESERVED GIO3_4 GIO1_2 R/W-0 R/W-0 LEGEND: R = Read only; -n = value after reset Table 9-16.
Page 136: Usb_Phy_Ctrl - Usb Phy Control
www.ti.com System Control Register Descriptions 9.10.15 USB_PHY_CTRL - USB PHY Control The USB_PHY_CTL register controls various features of the USB PHY. Figure 9-14. USB_PHY_CTRL - USB PHY Control RESERVED RESERVED DATAPOL PHYCLKSRC PHYCLKGD R/W-0 R/W-0 SESNDEN VBDTCTEN VBUSENS PHYPLLON RESERVED VPSS_ OTGPDWN PHYPDWN...
Page 137 www.ti.com System Control Register Descriptions Table 9-17. USB_PHY_CTRL - USB PHY Control Field Descriptions (continued) Field Value Description PHYPDWN USB PHY power down control PHY powered PHY power off SPRUFB3 – September 2007 System Control Module Submit Documentation Feedback...
Page 138: Misc - Miscellaneous Control
www.ti.com System Control Register Descriptions 9.10.16 MISC - Miscellaneous Control The MISC register include miscellaneous control functions. Figure 9-15. MISC - Miscellaneous Control RESERVED RESERVED RESERVED TIMER2_WDT DEV_SPEED PLL1_POSTDIV AIM_WAIST R/W-1 R-eFuse R/W-1 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 9-18.
Page 139: Mstpri0 - Master Priorities 0
www.ti.com System Control Register Descriptions 9.10.17 MSTPRI0 - Master Priorities 0 The MSTPRI0 registers provides control of the Bus Masters' DMA Priorities. Figure 9-16. MSTPRI0 - Master Priorities 0 RESERVED RESERVED ARM_CFGP RESV ARM_DMAP R/W-0x1 R/W-0x1 LEGEND: R = Read only; -n = value after reset Table 9-19.
Page 140: Mstpri1 - Master Priorities 1
www.ti.com System Control Register Descriptions 9.10.18 MSTPRI1 - Master Priorities 1 The MSTPRI0 registers provides control of the Bus Masters' DMA Priorities. Figure 9-17. MSTPRI1 - Master Priorities 1 RESERVED RESERVED USBP RESERVED R/W-0x4 LEGEND: R = Read only; -n = value after reset Table 9-20.
Page 141: Vpss_Clk_Ctrl - Vpss Clock Mux Control
www.ti.com System Control Register Descriptions 9.10.19 VPSS_CLK_CTRL - VPSS Clock Mux Control The VPSS Clock multiplexing control is provided by the VPSS_CLK_CTRL register. Figure 9-18. VPSS_CLK_CTRL - VPSS Clock Mux Control RESERVED RESERVED RESERVED VENC_CLK_SRC DACCLKEN VENCLKEN PCLK_INV VPSS_MUXSEL R/W-0 R/W-0 R/W-0 R/W-0...
Page 142: Deepsleep - Deep Sleep Mode Configuration
www.ti.com System Control Register Descriptions 9.10.20 DEEPSLEEP - Deep Sleep Mode Configuration The DEEPSLEEP register provides configuration for the Deep SLeep powerdown mode. Figure 9-19. DEEPSLEEP - Deep Sleep Mode Configuration SLEEP SLEEP RESERVED ENABLE COMPLET R/W-0 COUNT RESV RESV VBUS VBUS FORC...
Page 143: Debounce[8] - De-Bounce For Gio[N] Input
www.ti.com System Control Register Descriptions 9.10.21 DEBOUNCE[8] - De-bounce for GIO[n] Input The DEBOUNCE[8] array of registers provide the controls for enabling and configuring Debounce for GIO[7:0] inputs. Figure 9-20. DEBOUNCE[8] - De-bounce for GIO[n] Input ENABLE RESERVED INTERVAL R/W-0 R/W-0 INTERVAL R/W-0...
Page 144: Vtpiocr - Vtp Io Control Register
System Control Register Descriptions 9.10.22 VTPIOCR - VTP IO Control Register VTPIOCR is used to calibrate the DDR2/mDDR I/O's. Refer to the TMS320DM355 DDR2/mDDR Peripheral Reference Guide (SPRUEH7) for information on how to calibrate the DDR2/mDDR I/O's using this register.
Page 145: Reset
SPRUFB3 – September 2007 Reset 10.1 Reset Overview There are five types of reset in DM355. The types of reset differ by how they are initiated and/or by their effect on the chip. Each type is briefly described in Table 10-1 and further described in the following sections.
Page 146: Types Of Reset
www.ti.com Types of Reset 10.3 Types of Reset 10.3.1 Power-On Reset (POR) POR totally resets the chip, including all modules, memories, and emulation circuitry. The following steps describe the POR sequence: 1. Apply power and clocks to the chip and drive TRSTN and RESETN low to initiate POR. 2.
Page 147: Max Reset
www.ti.com Default Device Configurations 10.3.3 Max Reset Max reset is like warm reset, except max reset is initiated by the Watchdog Timer (WDT) or by an IcePick emulation command. For debug, max reset allows an ARM emulator to initiate chip reset using an IcePick emulation command while remaining active during and after the reset sequence.
Page 148: Pll Configuration
www.ti.com Default Device Configurations Note: The device configuration pins are multiplexed with AEMIF pins. After the device configuration pins are sampled at reset, they automatically change to function as AEMIF pins. Pin multiplexing is described in Chapter Table 10-3. Device Configuration Default Setting Device (by internal...
Page 149: Aemif Configuration
www.ti.com Default Device Configurations 10.4.5 AEMIF Configuration 10.4.5.1 AEMIF Pin Configuration The input pins AECFG[3:0] determine the AEMIF configuration immediately after reset. Use AECFG[3:0] to properly configure the pins of the AEMIF. Refer to the section on pin multiplexing in Chapter Also, see the Asynchronous External Memory Interface (AEMIF) Peripheral Reference Guide (SPRU710) for more information on the AEMIF.
Page 150: Boot Modes
SPRUFB3 – September 2007 Boot Modes 11.1 Boot Modes Overview The DM355 ARM can boot from either Async EMIF (AEMIF/OneNand) or from ARM ROM, as determined by the setting of the device configuration pins BTSEL[1:0]. The BTSEL[1:0] pins can define the ROM boot mode further as well.
Page 151: Boot Modes Overview
www.ti.com Boot Modes Overview loading UBL) – Supports booting from 8-bit NAND devices (16-bit NAND devices are not supported) – Supports 4-bit ECC (1-bit ECC is not supported) – Supports NAND flash that requires chip select to stay low during the tR read time •...
Page 152: Functional Block Diagram
www.ti.com ARM ROM Boot Modes 11.1.2 Functional Block Diagram The general boot sequence is shown in Figure 11-2. Figure 11-2. Boot Mode Functional Block Diagram Reset Boot mode Internal ROM Boot mode Boot from Boot from UART NAND flash Boot OK ? Boot OK ? Boot from MMC/SD...
Page 153: Nand Boot Flow
www.ti.com ARM ROM Boot Modes First, the device ID of the NAND device is read from the device, and then any necessary information (such as the block and page sizes, etc.) are obtained from the device information table in the RBL. The device information in the RBL is based on the list of supported NAND devices.
Page 154: Nand Ubl Descriptor
www.ti.com ARM ROM Boot Modes The NAND User boot loader UBL descriptor format is described in Table 11-1. Table 11-1. NAND UBL Descriptor Page 0 Address 32-Bits Description 0xA1AC EDxx Magic number (0xA1ACEDxx) Entry Point Address of UBL Entry point address for the user boot-loader (absolute address) Number of pages in UBL Number of pages (size of user boot-loader in number of pages) Starting Block # of UBL...
Page 155: Bit Ecc Format And Bit 10 To 8-Bit Compression Algorithm
www.ti.com ARM ROM Boot Modes Figure 11-4. 4-Bit ECC Format and Bit 10 to 8-Bit Compression Algorithm Algorithm to store 10 bit codes in 8 bit words Data //Convert eight 10-bit codes to ten 8-bit words: Syndrome0 = syndromes10[0] & 0xFF; Syndrome1 = ((syndromes10[1] &...
Page 156: Bit Ecc Format For 2048+64 Byte Page Size
www.ti.com ARM ROM Boot Modes Figure 11-5. 4-Bit ECC Format for 2048+64 Byte Page Size Data 512+16 byte Syndrome Data 512+16 byte 1 Page Syndrome (2048+64 Data byte) 512+16 byte Syndrome Data 512+16 byte Syndrome 11.2.1.1 NAND Boot Detailed Flow An overview of the NAND Boot process is shown in the flow chart in Figure 11-6 and exemplified in...
Page 157 www.ti.com ARM ROM Boot Modes • May span multiple blocks • Total bytes must be less than or equal to 30KByte total (size of IRAM - ~2KB stack space) – Starting Block of UBL: • May be the same block as UBL descriptor –...
Page 158: Nand Boot Mode Flow Chart
www.ti.com ARM ROM Boot Modes Figure 11-6. NAND Boot Mode Flow Chart NAND boot mode Read page 0 Start searching for valid magic number of block M in page 0 of block M=1. If a failure, read (M++) next consecutive block up to block M=24. Attempt ECC correction correction...
Page 159: Arm Nand Rom Boot Loader Example
www.ti.com ARM ROM Boot Modes Figure 11-7. ARM NAND ROM Boot Loader Example Page Block CIS/IDI Found magic number User boot loader (UBL) definition 32-bits Page 0 addr UBL magic number ID 0xA1ACED00 Page Block UBL Def Entry point addr of UBL 0x00002100 UBL start addr Number of pages in UBL...
Page 160: Descriptor Search For Arm Nand Boot Mode
www.ti.com ARM ROM Boot Modes Figure 11-8. Descriptor Search for ARM NAND Boot Mode Page 0 Block CIS/IDI Page 0 Block Start searching at Block 1, Page 0 If no magic number found or Page 0 Block NAND read error detected If no magic number found or Page 0 Block...
Page 161 www.ti.com ARM ROM Boot Modes Table 11-3. NAND IDs Supported (continued) Number of pages per Bytes per page Block shift value Device ID block (including extra data) (For address) No. of address cycles 0xE6 512+16 0x39 512+16 0x6B 512+16 0x73 512+16 0x33 512+16...
Page 162: Mmc/Sd Boot Mode
www.ti.com ARM ROM Boot Modes • The RBL will copy a fast UBL from NAND to ARM internal memory and then transfer control to the fast UBL. The fast UBL will reinitialize the DM355, bring mDDR out of self-refresh, and branch to an entry point in mDDR.
Page 163: Mmc/Sd Boot Mode Overview
www.ti.com ARM ROM Boot Modes Figure 11-9. MMC/SD Boot Mode Overview Power on Run the ROM boot loader in ROM Copy the user boot loader in MMC/SD to IRAM ROM boot loader Jump to user boot loader entry point in IRAM Copu user MAIN program in MMC/SD...
Page 164: Mmc/Sd Ubl Descriptor
www.ti.com ARM ROM Boot Modes The MMC/SD User boot loader UBL descriptor format is described in Table 11-4. Table 11-4. MMC/SD UBL Descriptor Page 0 Address 32-Bits Description 0xA1AC EDxx Magic number (0xA1ACEDxx) Entry Point Address of UBL Entry point address for the user boot-loader (absolute address) Number of blocks in UBL Number of blocks (size of user boot-loader in number of blocks) Starting Block # of UBL...
Page 165: Mmc/Sd Boot Mode Flow Chart
www.ti.com ARM ROM Boot Modes Figure 11-10. MMC/SD Boot Mode Flow Chart MMC/SD boot mode Start searching for valid magic number block M=1. Read block M If a failure has occured, read next consecutive (M++) block up to M=24 Magic number OK When a valid UBL signature is found, the Write block...
Page 166: Arm Mmc/Sd Rom Boot Loader Example
www.ti.com ARM ROM Boot Modes Figure 11-11. ARM MMC/SD ROM Boot Loader Example User boot loader (UBL) definition Found magic number Byte addr 32-bits Block UBL def 0xA1ACED00 UBL magic number ID Entry point addr of UBL 0x00002100 UBL start addr UBL block 1 0x00000013 19 blocks...
Page 167: Uart Boot Mode
www.ti.com ARM ROM Boot Modes Figure 11-12. Descriptor Search for ARM MMC/SD Boot Mode Start searching at block 0 Block If no magic number found or MMC/SD read error detected Block If no magic number found or MMC/SD read error detected Block If no magic number found or MMC/SD read error detected...
Page 168: Uart Boot Mode Handshake
www.ti.com ARM ROM Boot Modes 11.2.3.1 DM355 and Serial Host Handshake If the state of BTSEL[1:0] pins reset is 11, then the UART boot mode executes as shown in Figure 11-13. The state of BTSEL[1:0] pins at reset is captured and stored in the bits BTSEL in the BOOTCFG register in the System Control Module.
Page 169: Uart Data Sequences
www.ti.com ARM ROM Boot Modes 11.2.3.2 UART Boot Loader Data Sequences The serial boot loader data sequences consist of handshake messages, UBL header, and the UBL payload itself. The messages use a fixed 8-byte ASCII string including a null string terminator. Short messages have leading spaces besides the null.
Page 170: Host Utility Timing
www.ti.com ARM ROM Boot Modes Table 11-7. Host Utility Data Format "^^^^ACK/0" Transfer Start Byte "^" "^" "^" "^" "A" "C" "K" "/0" ——→ Checksum "9af944c9" Transfer ——→ Table 11-8. CRC32 Table Transfer crc32_table[1024] = {0x01234567L, 0x89ABCDEFL..} Start Byte "0" "1"...
Page 171: Power Management
SPRUFB3 – September 2007 Power Management 12.1 Overview The DM355 is desigend for minimal power consumption. There are two components to power consumption: active power and leakage power. Active power is the power consumed to perform work and scales with clock frequency and the amount of computations being performed. Active power can be reduced by controlling the clocks in such a way as to either operate at a clock setting just high enough to complete the required operation in the required timeline or to run at a clock setting until the work is complete and then drastically cut the clocks (e.g.
Page 172: Clock Management
www.ti.com Clock Management 12.3 Clock Management 12.3.1 Module Clock Disable The module clock disable feature allows software to disable individual module clocks, in order to reduce a module's active power consumption to 0. DM355 is designed in full static CMOS; thus, when a module clock stops, the module's state is preserved.
Page 173: System Sleep Modes
www.ti.com System Sleep Modes Note: The ARM interrupt controller and the module sourcing the wakeup interrupt (e.g., GIO or WDT) must not be disabled, or the device will never wake up. For more information on this sleep mode, refer to the ARM926EJ-S Technical Reference Manual, which is available from ARM Ltd.
Page 174: I/O Management
The DM355’s DDR controller supports self-refresh and power down. This allows you to put the DDR device in its self-refresh or power down states for power savings. See the TMS320DM355 DMSoC DDR2/Mobile DDR (DDR2/mDDR) Memory Controller Reference Guide (SPRUEH7) for detailed information on DDR self-refresh and power down.
Page 175 TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products...

Texas Instruments TMS320DM355 User Manual

Preface

1 Introduction

2 ARM Subsystem Overview

3 ARM Core

4 Memory Mapping

5 Device Clocking

6 PLL Controllers (Pllcs)

7 Power and Sleep Controller

8 Interrupt Controller

9 System Control Module

10 Reset

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Summary of Contents for Texas Instruments TMS320DM355