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TMS320DM355
Digital Media System-on-Chip (DMSoC)
SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007
5 Peripheral Information and Electrical Specifications
5.1
Parameter Information Device-Specific Information
42 Ω
4.0 pF
A.
The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its
transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to
produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to
add
or
subtract
Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the
device pin.
The load capacitance value stated is only for characterization and measurement of AC timing signals. This
load capacitance value does not indicate the maximum load the device is capable of driving.
5.1.1 Signal Transition Levels
All input and output timing parameters are referenced to V
V
= 1.65 V. For 1.8 V I/O, V
ref
Figure 5-2. Input and Output Voltage Reference Levels for AC Timing Measurements
All rise and fall transition timing parameters are referenced to V
V
MAX and V
MIN for output clocks.
OL
OH
Figure 5-3. Rise and Fall Transition Time Voltage Reference Levels
94
Peripheral Information and Electrical Specifications
Tester Pin Electronics
3.5 nH
Transmission Line
Z0 = 50 Ω
(see note)
1.85 pF
the
transmission
line
delay
Figure 5-1. Test Load Circuit for AC Timing Measurements
= 0.9 V.
ref
Data Sheet Timing Reference Point
(2
ns
or
longer)
from
for both "0" and "1" logic levels. For 3.3 V I/O,
ref
MAX and V
IL
V
= V
ref
IH
V
= V
ref
IL
www.ti.com
Output
Under
Test
Device Pin
(see note)
the
data
sheet
timings.
V
ref
MIN for input clocks,
IH
MIN (or V
MIN)
OH
MAX (or V
MAX)
OL
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