Bank Interleaved Memory With Two Memory Blocks - Texas Instruments TMS320C6000 Programmer's Manual

Figure 6–23. 4-Bank Interleaved Memory With Two Memory Blocks
Memory
0 1
block 0
8 9
8N 8N + 1
Bank 0
Memory 8M 8M + 1
block 1
Bank 0
If each array in a loop resides in a separate memory block, the 2-cycle loop
in Example 6–61 on page 6-111 is sufficient. This section describes a solution
when two arrays must reside in the same memory block.
Optimizing Assembly Code via Linear Assembly
2 3 4
10 11 12
8N + 2 8N + 3 8N + 4
Bank 1 Bank 2
8M + 2 8M + 3 8M + 4
Bank 1
Memory Banks
5 6
13 14
8N + 5 8N + 6 8N + 7
Bank 3
8M + 5 8M + 6 8M + 7
Bank 2 Bank 3
7
15
6-119