Supernova - IBM Power Systems 775 Manual

1.4.6 SuperNOVA

SuperNOVA is the second member of the fourth generation of the IBM Synchronous Memory
Interface ASIC. It connects host memory controllers to DDR3 memory devices.
SuperNOVA is used in a planar configuration to connect to Industry Standard (I/S) DDR3
RDIMMs. SuperNOVA also resides on a custom, fully buffered memory module that is called
the SuperNOVA DIMM (SND). Fully buffered DIMMs use a logic device, such as SuperNOVA,
to buffer all signals to and from the memory devices.
As shown in Figure 1-9, SuperNOVA provides the following features:
Cascaded memory channel (up to seven SNs deep) that use 6.4-Gbps, differential ended
(DE), unidirectional links.
Two DDR3 SDRAM command and address ports.
Two, 8 B DDR3 SDRAM data ports with a ninth byte for ECC and a tenth byte that is used
as a locally selectable spare.
16 ranks of chip selects and CKE controls (eight per CMD port).
Eight ODT (four per CMD port).
Four differential memory clock pairs to support up to four DDR3 registered dual in-line
memory modules (RDIMMs).
Data Flow Modes include the following features:
Expansion memory channel daisy-chain
4:1 or 6:1 configurable data rate ratio between memory channel and SDRAM domain
Figure 1-9 Memory channel
SuperNOVA uses a high speed, differential ended communications memory channel to link a
host memory controller to the main memory storage devices through the SuperNOVA ASIC.
The maximum memory channel transfer rate is 6.4 Gbps.
The SuperNOVA memory channel consists of two DE, unidirectional links. The downstream
link transmits write data and commands away from the host (memory controller) to the
SuperNOVA. The downstream includes 13 active logical signals (lanes), two more spare
lanes, and a bus clock. The upstream (US), link transmits read data and responses from the
SuperNOVA back to the host. The US includes 20 active logical signals, two more spare
lanes, and a bus clock.
Although SuperNOVA supports a cascaded memory channel topology of multiple chips that
use daisy chained memory channel links, Power 775 does not use this capability.
Chapter 1. Understanding the IBM Power Systems 775 Cluster
17