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When the same code is run in Burst mode, every fourth external
fetch is replaced by four fetches, and the other fetches are cache hits.
In a hit state the internal fetch and instruction execution take (in this
example) 1 cycle. This cycle may be in parallel to an external data
access, so the total cycle count of such an instruction will be equal to
the cycle count of the external data access. If an instruction is a hit,
with no memory accesses that should be performed from previous
instructions, it may be executed in parallel to the accesses starting in
the previous instruction. This is why some entries in the cycle count
table are empty.
As could be seen from the table, in both cases, the total cycle count
in this example depends only on the external accesses. The cut in
external access time achieved by using the burst mode is a net
increase in performance.
5.2
MEMORY SWITCH
Each chip has a fixed amount of internal RAM, divided between x, y
and p spaces. This architecture allows fetching an instruction in
parallel to two data moves, but does not allow the use of data space
for program instructions and vice-versa. Some members of the
DSP56300/600 families support a Memory Switch mode, in which
the user may chose between two predefined internal memory
partitions, one with more Program RAM at the expense of the X and
Y data RAM.
Memory switching is not available for some chips and revisions.
Please refer to the user's manual of the chip you are using for
information on the memory map.
Figure 5-1 on page 5-10 depicts the DSP56302 memory map as an
example. The upper parts of the shaded memory areas are switched
between data and program spaces.
Note: In Memory Switch mode, the cacheable program memory
module changes its location in the program memory map, so
that it will always occupy the top-most internal program
memory addresses.
MOTOROLA
Optimizing DSP56300/DSP56600 Applications
Instruction Cache and Memory Features
Memory Switch
5-9
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