Optimizing The Code For Best Performance 1-7 1.4.3 - Motorola DSP56600 Manual

• Section 4—Using the DMA
– How to reduce core MIPS by using the DMA
– How to service peripherals using the DMA
– How to use slow, inexpensive memory chips without
loosing performance
– How to handle complex data structures by using the
DMA
• Section 5—Instruction Cache and Other Memory Features
– Basic instruction cache tutorial
– Data organization for efficient sector allocation
– Sector locking for critical loops
– Flushing the cache after task switching.
– Burst mode for DRAMs
– Memory banks between program and data
– Using the bootstrap ROM
1.4.2 Optimizing the Code for Best Performance
The next two sections include general explanation of the various
pipeline stall conditions and how they can be avoided in order to
get faster execution times. In addition, some observations on the
instruction set are included along with recommended usage for
optimization purposes.
• Section 6—Pipeline Interlocks
– Description of the various types of interlocks
– Ways to avoid each type of interlock
– Program flow and control
– Understanding timing of conditional change of flow
– How to reorder code at the end of DO loops
– When to use the repeat instruction
• Section 7—Compact Opcode Use
MOTOROLA Optimizing DSP56300/DSP56600 Applications
Introduction
Application Note Structure
1-7