B.2 Jtag Port Features - Motorola DSP56600 Manual

Debug and Test Support
JTAG Port Features
B-2 Optimizing DSP56300/DSP56600 Applications
• Trace one (single stepping) or up to 256 instructions
• Save or restore the current pipeline state of the DSP core
• Display the contents of the real-time instruction trace buffer
• Return to user mode from Debug mode
• Set-up breakpoints without being in Debug mode
• All OnCE events can either force the chip into Debug mode
or force a vectored interrupt, based on the users needs

B.2 JTAG PORT FEATURES

The JTAG port conforms to the IEEE 1149.1a-1993 IEEE Standard
Test Access Port and Boundary Scan Architecture specification
defined by the Joint Test Action Group (JTAG). Five dedicated pins
interface to a Test Access Port (TAP). The TAP uses a boundary scan
technique to test the interconnections between integrated circuits
after they are assembled onto a printed circuit board. Boundary
scan allows a tester to observe and control signal levels at each
component pin through a shift register placed next to each pin. This
is important for testing continuity and determining if pins are stuck
at a one or zero level.
The JTAG port has the following capabilities:
• Perform boundary scan operations to test circuit-board
electrical continuity
• Bypass the DSP for a given circuit-board test by replacing the
boundary scan register with a single bit register
• Sample the DSP system pins during operation, and
transparently shift out the result in the boundary scan
register; pre-load values to output pins prior to invoking the
EXTEST instruction
• Disable the output drive to pins during circuit-board testing
• Provide a means of accessing the OnCE controller and
circuits to control a target system
• Query identification information (manufacturer, part
number, and version) from a DSP
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