Cache Sectors - Motorola DSP56600 Manual

Instruction Cache and Memory Features
The Instruction Cache
preceding it. The DO instruction, being a 2-word instruction, suffers
the wait states of two fetches
Instructions in a loop are re-fetched on each iteration, with the wait
states inserted each time. The column in Table 5-1 labeled "hit
cycles" is the number of cycles needed for the execution of the
instructions if they were run from internal memory or were cache
hits. The column "external miss cycles" is the number of cycles
needed if they were run from a 3-wait state memory with cache
disabled, or fetched with a "miss".
If the same code is run with the cache enabled, the first loop
iteration will take the same number of cycles as with the cache
disabled, since the instructions are "misses" and should be fetched
from the external memory. From the second iteration onwards, the
instructions are "hits" and, therefore, execution time will be one
cycle per instruction. At the end of the loop there will be cache
misses once more. If this code section will be executed again (e.g., if
it was a part of a subroutine), then it will be all "hits" and run
according to the 3N + 10 formula—as if it were in the internal
memory.
There is no penalty for a cache miss, above the needed wait states
associated with the external access itself. All cache operations are
done in parallel to program execution, without any performance
cost.
5.1.1

Cache Sectors

A chip in the DSP56300 family may be factory-configured to
support a 1 K or 2 K cache, or none. See the user's manual for the
specific configuration of the chip you are using. In this section,
when data that depends on the size of the cache is given, the 1 K
cache data is written first followed by the data for 2 K cache written
in parentheses.
The 1 K (2 K) cache is logically divided into eight sectors, each 128
(256) words long. Accordingly, the cache views an instruction
address as comprised of two parts: bits 23:8 (23:9), labeled the "tag
field", and bits 7:0 (8:0) labeled the "vbit field". During cache
operation, a sector is allocated to store program words with the
same tag field in their address. This tag field is stored in a tag
register associated with each sector. It follows, therefore, that the
cache cannot store 1024 (2048) instructions originating from
MOTOROLA Optimizing DSP56300/DSP56600 Applications 5-3