Chapter 2
Device Overview
Duplicate Count Prevention
NI 660x User Manual
Counter
Source
PFI 38
at Input To ASIC
PFI 38
Synchronized at Pad
PFI 38
at CTR 0 GATE
PFI 38
at CTR 1 GATE
Sampled
GATE at Ctr0
Sampled
GATE at Ctr1
Figure 2-3. Counters 0 and 1 at Gate Edge on PFI 38 at the Same Time
Duplicate count prevention (or synchronous counting mode) ensures that a
counter returns correct data in applications that are a slow or non-periodic
external source. Duplicate count prevention applies only to buffered
counter applications such as measuring frequency or period.
For such buffered applications, the counter should store the number of
times an external source pulses between rising edges on the Gate signal.
2-4
1/2 Cycles
1/4 Cycle
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