AT&T 3B2 Off-Line Diagnostic Manual page 485

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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Phase Descriptions
Phase #1 Tests
Test Numbers:
1 and 2
Function:
These tests confirm that the Inhibit Alarms bit of the CSR can be set and
cleared.
Procedure:
Determine the address of the board under test. Then set the 'inhib_alrms' bit
of the CSR. Read the CSR confirming that it is set. Clear the bit by reading
the ' enb_alrms' bit of the CSR. Read the CSR confirming that the bit is
cleared.
Hardware Tested:
The AIC CSR is tested.
Data Returned:
The failing test number (last number displayed on the system console prior to
failure) is returned.
Notes:
The Inhibit Alarms bit is set at the end of this test to enable the testing of the
other CSR bits without side effects.
Test Numbers:
3 and 4
Function:
These tests confirm that the Software Minor (SWMINOR) Alarm bit of the CSR
can be set and cleared.
Procedure:
Set the SWMINOR Alarm bit of the CSR. Read the CSR confirming that it is
set. Clear the bit by reading the' clr_swminor' bit of the CSR. Read the CSR
confirming that the bit is cleared.
Hardware Tested:
The AIC CSR is tested.
Data Returned:
The failing test number (last number displayed on the system console prior to
failure) is returned.
Notes:
None
Test Numbers:
5 and 6
Function:
These tests confirm that the Software Major (SWMAJOR) Alarm bit of the CSR
can be set and cleared.
Procedure:
Set the SWMAJOR Alarm bit of the CSR. Read the CSR confirming that it is
set. Clear the bit by reading the '
clr~wmajor'
bit of the CSR. Read the CSR
confirming that the bit is cleared.
Hardware Tested:
The AIC CSR is tested.
Data Returned:
The failing test number (last number displayed on the system console prior to
failure) is returned.
Notes:
None
REMOTE MANAGEMENT DIAGNOSTICS 10-3

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