AT&T 3B2 Off-Line Diagnostic Manual page 42

Version 2 Hardware System Board Diagnostics
This section contains a description of the diagnostic phases and tests for two different Version 2
hardware System Boards (SBDs). UNIX System V Release 2.0.4 and subsequent releases support the
Math Accelerator Unit (MAU) for 3B2/310 and 400 computers, but the previous releases do not. Three
normal phases are used to diagnose the MAU. They are shown as Phases 4, 5, and 6 for Release 2.0.4
and subsequent releases in the following table. These phases replace the original normal phases of the
same numbers for Release 2.0. As a result, these additional phases cause the original phase numbers to
be incremented for Release 2.0. To reduce duplication, the phase numbers for the version that does not
support the MAU (Release 2.0) are enclosed in parentheses in the phase number headings in this
section. The following table further illustrates this relationship, and it can be used for reference:
PHASE DESCRIPTION RELEASE 2.0 RELEASE 2.0.4
CPU #2 Normal 1 1
CPU #3 Normal
2
2
CPU #4 Normal 3 3
MAU #1 Normal -
4
MAU #2 Normal
-
5
MAU #3 Normal
-
6
Memory Management #1 Normal
(4) 7
Memory Management #2 Normal (5) 8
Memory Management #3 Normal
(6)
9
Memory Management #4 Normal
(7) 10
Dynamic Memory Demand (8) 11
Nonvolatile Memory Interactive
(9) 12
Sanity /Interval Timer Normal
(10) 13
Control and Status Register Normal
(11)
14
DUART Interactive
(12) 15
Permanent Interrupt Demand (13) 16
CPU Interrupt System Normal
(14)
17
Direct Memory Controller Normal
(15) 18
Floppy Disk Interface Interactive (16) 19
Fast Hard Disk Normal
(17)
20
Extended Hard Disk Demand
(18)
21
Time-of-Day Clock Interactive
(19) 22
Hard Disk Media Check Interactive (20) 23
The SBD is a highly integrated circuit board that serves as the primary element of the
3B2 computer. The following components are found on the SBD:
• MAU (optional for Release 2.0.4 and subsequent releases)
• Memory Management Unit (MMU)
• WE® 32002 Microprocessor [includes Central Processing Unit (CPU) and MMU]
• Dynamic Random Access Memory (DRAM) Controller
• Direct Memory Access (DMA) Subsystem [includes Direct Memory Access Controller (DMAC),
Hard Disk Controller, Floppy Disk Controller, and Universal Asynchronous Receiver/Transmitter
(UART)]
3-2 OFF-LINE DIAGNOSTIC MANUAL