AT&T 3B2 Off-Line Diagnostic Manual page 185

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Phase Descriptions
Phase #1 Tests
Test Number:
Function:
Procedure:
1
This test checks all memory accesses on a word basis, checking for shorted
address lines.
Perform the following test algorithm:
Let Au be the memory address u.
Let
O<=u<2**n where n is the bit size.
E - indicates an element exists in the set.
Tl = {Aulu=O (modulo 3)}
T2 = {Aulu=1 (modulo 3)}
T3 = {Aulu=2 (modulo 3)}.
Step 1: Write the all 0 word, WO, at all locations
Aj E Tl and Ak E T2.
Step 2: Write the all 1 word, WI, at all locations
Ai E TO.
Step 3: Read all locations Aj E Tl
if output = WO no fault indicated.
Step 4: Write the all 1 word, WI, at all locations
Aj E Tt.
Step 5: Read all locations Ak E T2
if output = WO no fault indicated.
Step 6: Read all locations Ai E TO and Aj E Tl
if output = WI no fault indicated.
Step 7: Write and then read the all 0 word
at all locations Ai E TO
if output = WO no fault indicated.
Step 8: Write and then read the all 1 word, WI,
at all locations Ak E T2
if output = WI no fault indicated.
Hardware Tested: The MPB memory is tested.
Data Returned: The failing address, the actual data, and the expected data are returned.
Notes: None
MULTIPROCESSOR DIAGNOSTICS 4-3