Version 3 Hardware System Board Diagnostics - - - - - - - - - - - - - - - - - - - - -
Test Numbers:
Function:
Procedure:
3 through 5
These tests check memory accesses.
Test 3 -
writes words and reads back as shorts. Increment address by 1000.
Test 4 -
writes two shorts and reads back as bytes. Increment address by
1000.
Hardware Tested:
The MMU PCACHE is tested.
Data Returned:
The failing address, the actual data, and the expected data are returned.
Notes:
None
Test Number:
6
Function:
This test checks the tag field of the PCACHE.
Procedure:
Access every entry in the cache, change a Tag bit, and repeat.
Hardware Tested:
The MMU PCACHE is tested.
Data Returned:
The failing address, the actual data, and the expected data are returned.
Notes:
None
Test Number:
7
Function:
This test checks the cache entry invalidation
Procedure:
Write a memory location through one MMU. Read it back. Write another
value into the same location with the other MMU. Verify that the entry in the
first MMU has changed.
Hardware Tested:
The MMU PCACHE is tested.
Data Returned:
The failing address, the actual data, and the expected data are returned.
Notes:
None
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