AT&T 3B2 Off-Line Diagnostic Manual page 241

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Phase Descriptions
The MMU setup is as follows (1 to 1 mapping, Section 0 only):
Phase #18 Tests
+--------------+
OxOOOOOOOO
I Low Core RAM I
I Read/Execute I
+--------------+
Ox00040000 Hardware
I R/W/Execute
+--------------+
Ox02000000 FW RAM AREA I
Ox02020000
Ox02040000
Ox02060000
Ox02070000
Ox0207ffff
I R/W/Execute I
+--------------+
Text Area
R/Execute
mmu.o
+--------------+
MMU Tables
I R/W/Execute
+--------------+
Program Spacel
vC_b6.o I
pcdata
I
(CACHEABLE) I
R/W/Execute I
+--------------+
Low Core Gatel
Tables I
Read/Write I
+--------------+
Test Number: 1
Segments 0 -
2 - 255
256
257
258
1\
259
v
Function: This test ensures that a double-bit error can be detected in virtual mode with
the MMU cache enabled.
Procedure: Inhibit Error Correction Coding (ECC). Fault the contents of a word.
Determine if a multiple-bit error occurred.
Hardware Tested: The Dynamic Memory Controller and MMU are tested.
Data Returned: The failing address, expected value, and actual the value read are returned.
Notes: None
MULTIPROCESSOR DIAGNOSTICS 4-59