General Hardware Functions; Clock Generation And Clock Supply; Clock Supply In Ertec 200; Figure 9: Clock Generation In Ertec 200 - Siemens ERTEC200 Manual

5

General Hardware Functions

5.1

Clock Generation and Clock Supply

The clock system of the ERTEC 200 basically consists of four clock systems that are decoupled through asynchronous
transfers.
This includes the following clock systems:
•
ARM946E-S together with AHB bus, APB bus, and IRT
•
LBU
•
JTAG Interface
•
PHYs and Ethernet MACs
5.1.1

Clock Supply in ERTEC 200

The required clocks are generated in the ERTEC 200 by means of internal PLL and/or through direct infeed.
The following table provides a detailed list of the clocks:
MODULE
ARM946ES
AHB/EMIF/ICU/LBU
IRTE (except MAC-MII)
APB
JTAG
MAC-MII/PHY

Table 17: Overview of ERTEC 200 Clocks

A PLL is integrated to generate the internal clocks in the ERTEC 200. The clock supply of the PLL takes place via the
following input pins:
25 MHz quartz at the inputs CLKP_A and CLKP_B or
25 MHz clock generator at input CLKP_A
The input clock is divided down by a factor of 12.5 MHz and fed into the PLL. The PLL generates a clock of 300 MHz,
which supplies the following clock generator. This generates all system clock required for the ERTEC 200.
The following figure shows the generation of the ERTEC 200 clocks:
CONFIG4
CONFIG3
CONFIG1
BYPASS_CLK
100MHz
25 CLKP_A
MHz
OS
C
CLKP_B
REF_CLK
25 MHz
SCAN_CLK(2:0)
SCANMODE

Figure 9: Clock Generation in ERTEC 200

Synchronous clocks CLK_50MHz and CLK_100MHz are used primarily in the ERTEC 200. For the ARM946E-S
processor, the required processor clock can be set via the configuration pins CONFIG[4:3]:
CONFIG4, CONFIG3 = 00
CONFIG4, CONFIG3 = 01
CONFIG4, CONFIG3 = 10
CONFIG4, CONFIG3 = 11
Copyright © Siemens AG 2007. All rights reserved.
Technical data subject to change
CLOCK SOURCE
PLL
PLL
PLL
PLL
JTAG-Clock
CLKP_A
PLL_IN
(12,5 MHz)
MUX
Divider
APLL
1:2
Lock - Timer
Power - up
(650us)
Lock
Monitor
ARM946 processor clock is 50 MHz.
ARM946 processor clock is 100 MHz.
ARM946 processor clock is 150 MHz.
Reserved
64
FREQUENCY
50/100/150 MHz (scalable)
50 MHz
50/100 MHz
50 MHz
0-10 MHz
25 MHz
BYPASS_CLK_IN
0
MUX
1
2
PLL_OUT
(300 MHz)
CLK_IN 0
MUX
1
Clock 0
Generation
0
MUX
1
1
Loc
k
Enable
HCLKEN
HCLKEN -
(ARM9)
Gen.
CLK_ARM
CLK_100
CLK_50
& &
CLK_UART
PLL_LOCK_STATE
PHY_CLK
ERTEC 200 Manual
Version 1.1.0