Video Input Signals; Figure 3. Video Input Timing Diagram; Table 5. Video Input Descriptions - Planar ICEBrite EL640.200-SK Series User Manual

Video Input Signals

The end of the top line of a frame is marked by VS, vertical sync signal as
shown in Figure . The end of each row of data is marked by HS. In non-buffered
mode, the VS signal may be independently set to a CMOS low level at any time
for longer than one frame period. During the time of VS inactivity the display is
blank. Halting VS results in a standby condition to minimize power usage in
buffered mode.
Horizontal Timing
HS
VCLK
VID0-3
Vertical Timing
VS
HS

Figure 3. Video Input Timing Diagram.

Table 5. Video Input Descriptions.

Num
1
2
3
4
5
6
7
8
9
10
11
12
* Non-buffered mode
10 EL640.200-SK Operations Manual (020-0348-00B)
9
1
First Line VID
Description
HS high time
HS low time
HS to VCLK
VID setup to VCLK
VID hold from VCLK
Video clock period
VCLK rise, fall time
VCLK low width
VCLK high width
VS high setup to HS low
VS hold after HS
VS low setup to HS high
HS period
VS period
Max frame rate*
3
4
5
Pixels: w x y z
10
11
2
Second Line VID Data
12
Symbol Min.
tHSh 125
tHSl 160
tHSsu 63
tVIDsu 100
tVIDhd 100
tVCLK 334 (200*)
tVCLKrf
tVCLKl 125
tVCLKh 125
tVShsu 100
tVShd 100
tVSlsu 140
tHS 53.6 (41.3*)
tVS 200 (101*)
239*
6
8
7
Pixels: a b c d
Max. Units
nsec
tVCLK
nsec
nsec
nsec
nsec
50 nsec
nsec
nsec
nsec
nsec
nsec
µsec
tHS
Hz