Motorola MVME5500 Installation And Use Manual page 56

MOTLoad Firmware
3
3-14
PCI Slave Image 3 Translation Offset = 4C000000
Sets LSI3_TO to indicate that the PCI memory address is to be
translated by 0x4C000000 before presentation on the VMEbus;
the result of the translation is: 0xB3FF0000 + 0x4C000000 =
0xFFFF0000, thus 0xFFFF0000 on the VMEbus.
PCI Slave Image 4 -7
These images are set to zeroes and thus disabled.
VMEbus Slave Image 0 Control = E0F20000
Sets VSI0_CTL to indicate that this image is enabled, write and
read posting is enabled, program/data and supervisory AM
coding, data width is 32 bits, VMEbus A32 address space, 64-bit
PCI transfers are disabled, PCI Lock on RMW cycles are disabled,
and to transfer into PCI memory space.
VMEbus Slave Image 0 Base Address Register = 00000000
Sets VSI0_BS to define the lower bound of VME addresses to be
transferred to the local PCI bus is 0x00000000.
VMEbus Slave Image 0 Bound Address Register = (Local
DRAM Size)
Sets VSI0_BD to define that the upper bound of VME addresses
to be equal to the size of local DRAM.
VMEbus Slave Image 0 Translation Offset = 00000000
Sets VSI0_TO to define that no translation of the VMEbus address
is to occur when transferred to the local PCI bus. According to the
CHRP map in use by MOTLoad, this will result in transfers to
local DRAM; that is, 0x00000000 on the VMEbus is 0x00000000
in local DRAM.
VMEbus Slave Image 1 - 7
These images are set to zeroes and thus disabled.
VMEbus Register Access Image Control Register =
00000000
The VRAI_CTL register is disabled.
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