Operation Mode; Overview; Reset Status - Panasonic MN103S User Manual

2.7 Operation Mode

2.7.1

Overview

This LSI provides only NORMAL mode as CPU operation mode. Low power consumption mode and other mode
are not provided.
2.7.2

Reset Status

External Reset Pin Input
If the reset pin (NRST) goes "L" level, the chip resets (initializes) itself internally and if the reset pin goes "H"
level, the wait for oscillation to stabilize starts by means of the 18-bit binary counter that is driven by the oscilla-
tion clock.
After the wait for oscillation stabilization is completed, the internal rest is released and the microcontroller enters
normal operation mode. Refer to [11.3.1 Oscillation Stabilization Wait Operation] for the wait for oscillation sta-
bilization.
Self Reset
Self reset is generated by setting the CHIPRST flag of the reset control register (RSTCTR) to from "0" to "1".
When the CHIPRST flag is "1", self reset is not generated even if "1" is set. The CHIPRST flag retains the value
even after self reset. Reset by the self reset is internal reset in the chip, so is not generated by the external reset
pin. Also, oscillation stabilization wait operation is not generated. Refer to [11.2.4 Reset Control Register] for
reset control register.
Table: 2.7.1 shows the status of the CPU registers right after the reset.
Table:2.7.1 CPU Register Status Right After the Reset
Register
Program counter
Data counter
Address register
Stack pointer
Multiply / divide register
Processor status word
Loop instruction register
Loop address register
Values
PC 0x40000000
D0 toD3 Undefined
A0 to A3 Undefined
SP Undefined
MDR Undefined
PSW 0x0000
LIR Undefined
LAR Undefined
Chapter 2
CPU Basics
Operation Mode II - 21