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Control basics
Power Input
Signal Inputs
Connectors
Luminance Control
Self Test
5
EL640.400-CB1/CB3 and –CD4 Operations Manual (020-0356-00A)
For ordering information of EL640-400-CB1 and other EL Displays, please visit http://www.eldisplays.com/EL640-400-CB1 or call +1-888-394-4998.
The EL panel has 640 transparent column electrodes crossing 400 row
electrodes in an X-Y fashion. Light is emitted when an AC voltage is applied at
a row- column intersection. The display operation is based on the symmetric,
line at a time data addressing scheme which is synchronized by the external
VS, HS, and VCLK input signals. The internal control signals and the high
voltage pulses for the column and row drivers are generated internally by the
control electronics. All control signal inputs are HCT compatible.
The required supply voltages for the display are +5 Vdc (Vcc1) for the logic and
either +12 Vdc (–CB1 and –CD4) or +24 Vdc (–CB3) (Vcc2) for the integrated
DC/DC converter. The high voltages needed for driving the display are
generated by the DC/DC converter from the Vcc2 input voltage.
For easy interfacing with VGA display controllers the data and control input
signals are VGA Feature Connector compatible. The display automatically
determines the mode of operation.
The control input J2 includes contacts for optional luminance control and
ENABLE signal to totally shut off the display when not in use (screen saver
function).
Table 2. Connectors.
J1
16-pin header
Mating
J2
4-pin header
Mating
The displays feature luminance control capability for users to set the
brightness of the display to meet the ambient lightning. The control function
is achieved by drawing a 0...1 mA current from LUMPOT1 to ground
(LUMPOT2). The luminance is at maximum level when the inputs are open. The
voltage level of LUMPOT1 (J2/1) is appr. 5.1 Vdc when disconnected.
The operation of the display can be easily checked using the SELFTST function.
Self test is performed when SELFTST jumper (PS1/1) is set or no data input is
present. During self test all pixels are lit except the left-most half of the
topmost row of the display.
ODU 511.066.003.016 or eq.
ODU 517.065.003.016 or eq.
Hirose DF1–4P–2.5DSA or eq.
Hirose DF1–4S–2.5 R 28 or eq.
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