Pll Controller Divider 1 Register (Plldiv1); Pll Controller Divider 1 Register (Plldiv1) Field Descriptions - Texas Instruments TMS320DM355 User Manual

PLL Controller Register Map

6.6.6 PLL Controller Divider 1 Register (PLLDIV1)

The PLL controller divider 1 register (PLLDIV1) is shown in
PLLC1 and PLLC2. PLLDIV1 controls the divider for SYSCLK1. The divider for PLLC1 SYSCLK1 is fixed
(cannot be changed) to (/2). The divider for PLLC2 SYSCLK1 is fixed (cannot be changed) to (/1). For
PLLC1 the divider must always be endabled (bit D1EN=1).
31
15 14
D1EN
R/W-1
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-9. PLL Controller Divider 1 Register (PLLDIV1) Field Descriptions
Bit Field
31-16 Reserved
15 D1EN
14-5 Reserved
4-0 RATIO
50 PLL Controllers (PLLCs)
Figure 6-8. PLL Controller Divider 1 Register (PLLDIV1)
Reserved
R-0
R-0
Value Description
Reserved
Divider enable for SYSCLK1. For PLLC1, this bit must always be set to 1. For PLLC2, this bit may
be set to 0 or 1.
0 Disable
1 Enable
Reserved
Divider ratio for SYSCLK1. Ratio value = RATIO + 1
Figure 6-8 and described in
Reserved
R-0
R-0
5
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Table 6-9 for
4
RATIO
R-1
R-0
SPRUFB3 – September 2007
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