Clock Management; Module Clock Disable; Module Clock Frequency Scaling; Pll Bypass And Power Down - Texas Instruments TMS320DM355 User Manual

Digital media system-on-chip (dmsoc) arm subsystem
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Clock Management

12.3 Clock Management

12.3.1 Module Clock Disable

The module clock disable feature allows software to disable individual module clocks, in order to reduce a
module's active power consumption to 0. DM355 is designed in full static CMOS; thus, when a module
clock stops, the module's state is preserved. When the clock is restarted, the module resumes operating
from the stopping point.
Note:
Stopping clocks to a module only affects active power consumption, it does not affect
leakage power consumption.
The power and sleep controller (PSC) controls module clock disable/enable. The procedure to
disable/endable module clocks is described in

12.3.2 Module Clock Frequency Scaling

Module clock frequency is scalable by bypassing the PLL's or by programming the PLL's multiply and
divide parameters. Reducing the clock frequency reduces the active switching power consumption linearly
with frequency. It has no impact on leakage power consumption.
Chapter 5
and
Chapter 6

12.3.3 PLL Bypass and Power Down

You can bypass the PLLs in DM355. Bypassing the PLLs sends the PLL reference clock to the post
dividers of the PLLC instead of to the PLL VCO output clock. The PLL reference clock is typically at 24
MHz; therefore, you can use this mode to reduce the core and module clock frequencies to very low
maintenance levels without using the PLL during periods of very low system activity. Furthermore, you can
power-down the PLL when bypassing it to save additional active power.
Chapter 5
and
Chapter 6

12.4 ARM Sleep Mode Management

12.4.1 ARM Wait-For-Interrupt Sleep Mode

The ARM module cannot have its clock turned off/on via the PSC module like other modules. However,
the ARM includes a special sleep mode called "wait-for-interrupt". When the wait-for-interrupt mode is
enabled, the clock to the CPU core is shut off and the ARM9 is completely inactive and only resumes
operation after receiving an interrupt. This mode does not affect leakage consumption.
You can enable the wait-for-interrupt mode via the CP15 register #7 using the following instruction:
• mcr p15, #0, rd, c7, c0, #4
The following sequence exemplifies how to enter wait-for-interrupt mode:
• Enable any interrupt (e.g., an external interrupt).
• Enable wait-for-interrupt mode using the following CP15 instruction:
– mcr p15, #0, rd, c7, c0, #4
The following sequence describes the procedure to wake up from the wait-for-interrupt mode:
• To wake up from the wait-for-interrupt mode, trigger any enabled interrupt (e.g., an external interrupt).
• The ARM's PC jumps to the IRQ vector and you must handle the interrupt in an interrupt service
routine (ISR).
Exit the ISR and continue normal program execution starting from the instruction immediately following the
instruction that enabled wait-for-interrupt mode: mcr p15, #0, r3, c7, c0, #4.
172
Power Management
Chapter
describe how to bypass the PLL's and how to program PLL frequency.
describe PLL bypass and PLL power down.
7.
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