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Note:
The ARM interrupt controller and the module sourcing the wakeup interrupt (e.g., GIO or
WDT) must not be disabled, or the device will never wake up.
For more information on this sleep mode, refer to the ARM926EJ-S Technical Reference
Manual, which is available from ARM Ltd. at www.arm.com.
12.5 System Sleep Modes
12.5.1 Deep Sleep Mode
Deep Sleep mode is a special power down mode in which all device clocks are stopped and the internal
oscillators are powered down. Registers and software are preserved. Thus, upon recovery, the program
may continue from where it left off with minimal overhead involved.
The Deep Sleep power down process works as follows:
• The ARM prepares for power down, typically after an external microcontroller notifies the ARM to
prepare for power down via an interrupt or serial communication.
• The ARM puts DRR in its self-refresh state. Program in DDR is preserved while DDR is in its
self-refresh state. In the case of mDDR, you may utilize Partial Array Self Refresh (PASR) for
additional power savings.
• To reduce the chip stand by power, it is advised to power down all the analog blocks (PLL cores, DDR
PHY DLL, DDR PHY, USB PHY, Video DAC, and CCP PHY).
• The ARM sets SLEEPENABLE in register DEEPSLEEP in the System module.
• The ARM informs the microcontroller that it has initiated Deep Sleep and begins polling
SLEEPCOMPLETE in DEEPSLEEP. During the recovery process, the ARM will wake up and detect
that SLEEPCOMPLETE has changed.
• The microcontroller transitions GIO0 from high to low and then continues to hold GIO0 low (for a
minimum of 500 ns) until it desires to exit Deep Sleep mode. The transition of GIO0 from high to low
creates a clock pulse advancing the Deep Sleep state machine. After this transition, all clocks are
stopped and then the internal oscillators are powered down.
• At this point, the DM355 is in Deep Sleep mode; power is reduced to a minimum.
The Deep Sleep wake up process works as follows:
• To initiate the wake up process, the microcontroller transitions GIO0 from low to high. This transition
creates a clock pulse advancing the Deep Sleep state machine. After this transition, the oscillators are
powered up and allowed to stabilize and then all clocks are restarted.
• The ARM detects that SLEEPCOMPLETE has changed
• The ARM clears SLEEPENABLE in register DEEPSLEEP
• The ARM brings DDR out of self refresh.
• At this point the ARM resumes normal operation. The ARM may branch to program code preserved in
DDR. Register states are preseved.
12.5.2 Fast NAND Boot Mode
Note:
Fast NAND boot mode is not supported in DM355. Fast NAND boot mode is superseded by
Deep Sleep mode. Please use Deep Sleep mode instead of Fast NAND boot mode. For
information on Deep Sleep mode, see
Fast NAND boot mode provides a power down mode similar to Deep Sleep mode. In Fast NAND boot
mode, the clocks are stopped and oscillators are powered down, however, to recover from the power
down state a reset and re-boot are required. Thus, unlike Deep Sleep mode, a reset and special boot are
required to recover from the power down state. Given the advantages of Deep Sleep mode, it is expected
that most users will use Deep Sleep mode rather than Fast NAND boot mode.
The Fast NAND Boot mode power down process works as follows:
SPRUFB3 – September 2007
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Section
12.5.1.
System Sleep Modes
Power Management
173
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