Appendix 2 Details Of Buffer Memory Areas - Mitsubishi Electric MELSEC-L Series LD40PD01 User Manual

Flexible high-speed i/o control module
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Appendix 2
Details of Buffer Memory Areas
This chapter describes the details on the buffer memory areas of the flexible high-speed I/O control module.
Latest error code (Un\G100)
This area stores the latest error code detected in the flexible high-speed I/O control module.
For details on the error codes, refer to the following.
Page 238 List of Error Codes
■How to clear an error
Turn on and off Error clear request (YF).
Cumulative number of write accesses to a flash ROM (Un\G102, Un\G103)
This area stores the cumulative number of writes to a flash ROM. When a hardware logic is written to the flash ROM of the
flexible high-speed I/O control module with the setting tool, the stored value is increased by one.
When the number of writes exceeds the allowable number of writes to the flash ROM (10000 times), the written hardware
logic data cannot be assured. To decrease the number of writes to the flash ROM, write hardware logics to the execution
memory for adjustment. After the adjustment is completed, write the hardware logic to the flash ROM.
SSI receive data monitor 0 (Un\G110, Un\G111)
Out of the data frames received from SSI encoder 0, the information for the number of bits specified with "Data Frame Length"
is stored in this area at the communication cycle of the SSI encoder.
The parity bit is not reflected to this area.
When the data frame length is smaller than 32 bits, the least significant bit of the data frame is stored in the bit 0 of Un\G110.
For details, refer to the following.
Page 114 SSI encoder block
A
SSI receive data monitor 1 (Un\G114, Un\G115)
Out of the data frames received from SSI encoder 1, the information for the number of bits specified with "Data Frame Length"
is stored in this area at the communication cycle of the SSI encoder.
The data to be stored in this area is the same as the one of SSI receive data monitor 0 (Un\G110, Un\G111).
APPENDICES
247

Appendix 2 Details of Buffer Memory Areas

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