If Filter, Amplifier, Dynamic Range Extension; If Digitizing Subsystem - Motorola MTM800 User Manual

THEORY OF OPERATION (TRANSCEIVER)

IF Filter, Amplifier, Dynamic Range Extension

The IF signal is routed via IF filter (FL5201) to IF amplifier Q5201. From there it is routed to the
Dynamic Range Extension circuitry which comprises Q5101, its bias components, and D5121. This
circuitry is required to maintain good receiver linearity over a wide range of incoming signal levels,
and prevent clipping of high level signals. This circuit avoids the use of fixed switchable attenuators
typically used in Automatic Gain Control (AGC) circuits.

IF Digitizing Subsystem

The IF Digitizing Subsystem is comprised of U5101. Here the IF signal is amplified and then mixed
with an internally generated 2nd LO signal to produce the second IF signal.
The 2nd IF signal is first processed by a variable gain amplifier and then converted to in-phase and
quadrature (I and Q) digital data samples by means of a bandpass sigma-delta analog-to-digital
converter.
The I and Q digital signals are formatted into a single serial bit stream and sent for further
processing to the Digital Signal Processor (DSP) (part of micro-processor) over the Synchronous
Serial Interface (SSI) data link.
An internal AGC circuit controls the gain of the variable gain amplifier (VGA) to ensure that the
maximum signal level into the ADC does not exceed a fixed analog ADC clip level and the rms
output level of the ADC is maintained at an established reference level.
An internal phase locked loop control circuit controls the frequency of voltage controlled oscillator
Q5180 which generates the 71.1 MHz 2
An internal phase locked loop control circuit controls the frequency of voltage controlled oscillator
Q5190 which generates the 18MHz sample clock frequency utilized by the ADC and decimation
filters.
Both phase locked loops derive their frequency reference from the buffered 16.8 MHz TCXO master
clock.
nd
LO injection frequency.
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